公开(公告)号：US20230197180A1

公开(公告)日：2023-06-22

申请号：US18080369

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Melissa I. Uribe

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G11C2211/5641

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

公开(公告)号：US11656937B2

公开(公告)日：2023-05-23

申请号：US17396522

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Aaron P. Boehm

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/15 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  H03M13/1575

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

公开(公告)号：US20220058295A1

公开(公告)日：2022-02-24

申请号：US17396531

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W. Dover ,  Steffen Buch

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: Methods, systems, and devices for safety and security for memory are described. In some examples, data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

公开(公告)号：US20250094649A1

公开(公告)日：2025-03-20

申请号：US18962771

申请日：2024-11-27

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W. Dover ,  Steffen Buch

IPC: G06F21/79 ,  G06F21/60 ,  G06F21/64 ,  G06F21/72 ,  G06F21/78 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: Methods, systems, and devices for safety and security for memory are described. In some examples, data associated with a memory device may be authenticated before an associated operation is executed. The data may be authenticated before it is executed at a volatile memory. The data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. At the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. Once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. If the first hash and second hash match, the data may be authenticated and one or more operations may be executed.

公开(公告)号：US12142335B2

公开(公告)日：2024-11-12

申请号：US18080369

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Melissa I. Uribe

IPC: G11C29/00 ,  G11C29/42

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

公开(公告)号：US12079078B2

公开(公告)日：2024-09-03

申请号：US17820120

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Steffen Buch

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/079

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

公开(公告)号：US20240289220A1

公开(公告)日：2024-08-29

申请号：US18658754

申请日：2024-05-08

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/0787

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.

公开(公告)号：US20220365845A1

公开(公告)日：2022-11-17

申请号：US17732289

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.

公开(公告)号：US20220066873A1

公开(公告)日：2022-03-03

申请号：US17396522

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15

Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.

公开(公告)号：US20250037782A1

公开(公告)日：2025-01-30

申请号：US18918743

申请日：2024-10-17

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Melissa I. Uribe

IPC: G11C29/42

Abstract: Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.