公开(公告)号：US20220222012A1

公开(公告)日：2022-07-14

申请号：US17144573

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Venkata Kiran Kumar Matturi ,  Tushar Chhabra ,  Sushil Kumar ,  Sharath Chandra Ambula

IPC: G06F3/06

Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

公开(公告)号：US20240319914A1

公开(公告)日：2024-09-26

申请号：US18626888

申请日：2024-04-04

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  Sushil Kumar ,  Venkata Kiran Kumar Matturi

IPC: G06F3/06 ,  G06F1/3234

CPC classification number: G06F3/0656 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/0679

Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

公开(公告)号：US20240231460A1

公开(公告)日：2024-07-11

申请号：US18536694

申请日：2023-12-12

Applicant: Micron Technology, Inc.

Inventor： Venkata Kiran Kumar Matturi ,  Sharath Chandra Ambula ,  Niraimathi N S

IPC: G06F1/28 ,  G06F1/10

CPC classification number: G06F1/28 ,  G06F1/10

Abstract: Information associated with a power consumption level of a set of components of a controller of a memory device is identified. A determination is made whether the information associated with the power consumption level satisfies one or more conditions. In response to the one or more conditions being satisfied, swallowing one or more clock pulses of a clock signal transmitted to at least one component of the set of components of the controller are swallowed.

公开(公告)号：US20230393747A1

公开(公告)日：2023-12-07

申请号：US18199422

申请日：2023-05-19

Applicant: Micron Technology, Inc.

Inventor： Venkata Kiran Kumar Matturi ,  Tara Gordon ,  Carla L. Christensen

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A controller can be directly coupled to a storage device and a memory device but not a host. The controller can monitor a plurality of regions of the memory device to determine whether the plurality of regions meet a criterion for fullness and responsive to determining that the plurality of regions meet the criterion, read data from the plurality of regions. The controller can, responsive to reading the data from the plurality of regions, store the data in the storage device and delete the data from the plurality of regions. The controller can further, responsive to storing the data, report to a host that the data has been moved from the memory device to the storage device. The controller can be implemented independent from the host.

公开(公告)号：US20230185727A1

公开(公告)日：2023-06-15

申请号：US18081468

申请日：2022-12-14

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/657

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

公开(公告)号：US11537527B2

公开(公告)日：2022-12-27

申请号：US17117907

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

IPC: G06F12/1009

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.