公开(公告)号：US09361128B2

公开(公告)日：2016-06-07

申请号：US14702412

申请日：2015-05-01

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Mehmet Iyigun ,  Yevgeniy Bak ,  Emily N. Wilson ,  Kirsten V. Stark ,  Sushu Zhang ,  Patrick L. Stemen ,  Brian E. King ,  Vasilios Karagounis ,  Neel Jain

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F1/3234 ,  G06F8/65 ,  G06F9/4418 ,  G06F9/442

Abstract: Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

公开(公告)号：US11609763B2

公开(公告)日：2023-03-21

申请号：US17510167

申请日：2021-10-25

Applicant: Microsoft Technology Licensing, LLC

Inventor： Hee Jun Park ,  Mehmet Iyigun

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/50 ,  G06F8/52 ,  G06F9/38

Abstract: Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

公开(公告)号：US11157279B2

公开(公告)日：2021-10-26

申请号：US16714626

申请日：2019-12-13

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Hee Jun Park ,  Mehmet Iyigun

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/50 ,  G06F8/52 ,  G06F9/38

Abstract: Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

公开(公告)号：US10579417B2

公开(公告)日：2020-03-03

申请号：US15497482

申请日：2017-04-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Yevgeniy M. Bak ,  Mehmet Iyigun ,  Christopher Peter Kleynhans ,  Syed A. Raza

IPC: G06F9/46 ,  G06F9/48

Abstract: The threads of a user mode process can access various different resources of a computing device, and such access can be serialized. To access a serialized resource, a thread acquires a lock for the resource. For each context switch in the computing device, a module of the operating system kernel checks for priority inversions, which is a situation in which a higher priority thread of the user mode process is waiting for (blocking on) a resource for which a lower priority thread has acquired a lock. In response to detecting such a priority inversion, the priority of the lower priority thread is boosted to allow the priority thread to execute and eventually release the lock that the higher priority thread is waiting for.

公开(公告)号：US10515019B1

公开(公告)日：2019-12-24

申请号：US16121488

申请日：2018-09-04

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mehmet Iyigun ,  Yevgeniy Bak ,  Landy Wang

IPC: G06F12/00 ,  G06F12/1009

Abstract: Updating aging information for memory backing a virtual address-backed virtual machine (VM). A virtual memory address (VA) is allocated, within a page table entry (PTE), to a process backing the VM. Based on memory access(es) by the VM to a non-mapped guest-physical memory address (GPA), the GPA is identified as being associated with the VA; an HPA is allocated for the accessed GPA; a host-physical memory address (HPA) is associated with the VA within the PTE; the GPA is associated with the HPA within a second level address translation (SLAT) structure entry; and an accessed flag is set within the SLAT entry. Aging information is updated, including identifying the SLAT entry; querying a value of the accessed flag in the SLAT entry; clearing the accessed flag in the SLAT entry without invalidating the SLAT entry; and updating aging information for the VA and/or HPA based on the queried value.

公开(公告)号：US10387313B2

公开(公告)日：2019-08-20

申请号：US14708525

申请日：2015-05-11

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Mehmet Iyigun ,  Yevgeniy Bak ,  Michael Fortin ,  David Fields ,  Cenk Ergan ,  Alex Kirshenbaum

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0831 ,  G06F11/14 ,  G06F12/0866 ,  G06F12/14 ,  G06F12/128 ,  G06F12/0862

Abstract: To ensure that the contents of a non-volatile memory device cache may be relied upon as accurately reflecting data stored on disk storage, it may be determined whether the cache contents and/or disk contents are modified during a power transition, causing cache contents to no longer accurately reflect data stored in disk storage. The cache device may be removable from the computer, and unexpected removal of the cache device may cause cache contents to no longer accurately reflect data stored in disk storage. Cache metadata may be managed during normal operations and across power transitions, ensuring that cache metadata may be efficiently accessed and reliably saved and restored across power transitions. A state of a log used by a file system may be determined prior to and subsequent to reboot of an operating system in order to determine whether data stored on a cache device may be reliably used.

公开(公告)号：US10380081B2

公开(公告)日：2019-08-13

申请号：US15476641

申请日：2017-03-31

Applicant: Microsoft Technology Licensing, LLC

Inventor： Kyle Thomas Brady ,  John C. Gordon ,  Benjamin M. Schultz ,  Ali Hajy ,  Morakinyo Korede Olugbade ,  Hari R. Pulapaka ,  Paul McAlpin Bozzay ,  Frederick Justus Smith ,  Mehmet Iyigun

IPC: G06F9/54 ,  G06F16/21 ,  G06Q10/10

Abstract: A container for one or more scheduled meeting is pre-built for the meeting prior to the meeting occurring. The container can be built in a variety of manners, including using both static and dynamic techniques. Dynamic techniques for building a container allows a pre-build system to include more pertinent data in the container whereas static techniques reduce computing workload and allow for pre-building containers for unscheduled meetings. A combination of static and dynamic building techniques can be applied using a layer repository. Alternately, a static base layer can be used and customized for scheduled meetings.

公开(公告)号：US10339295B2

公开(公告)日：2019-07-02

申请号：US15221953

申请日：2016-07-28

Applicant: Microsoft Technology Licensing, LLC

Inventor： Jon Robert Berry ,  Youssef Barakat ,  Yevgeniy M. Bak ,  Mehmet Iyigun ,  Pedro Miguel Sequeira de Justo Teixeira

IPC: G06F21/46 ,  G06F21/44 ,  G06F9/50

Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.

公开(公告)号：US20190012182A1

公开(公告)日：2019-01-10

申请号：US16111187

申请日：2018-08-23

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mehmet Iyigun ,  Yevgeniy Bak ,  Emily N. Wilson ,  Kristen V. Stark ,  Sushu Zhang ,  Patrick L. Stemen ,  Brian E. King ,  Vasilios Karagounis ,  Neel Jain

IPC: G06F9/4401

CPC classification number: G06F9/4406 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/442

Abstract: Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

公开(公告)号：US10037270B2

公开(公告)日：2018-07-31

申请号：US14685977

申请日：2015-04-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： Yevgeniy M. Bak ,  Mehmet Iyigun ,  Landy Wang ,  Arun U. Kishan

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/1009 ,  G06F9/50

CPC classification number: G06F12/023 ,  G06F9/5016 ,  G06F12/08 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/657

Abstract: A set of memory pages from a working set of a program process, such as at least some of the memory pages that have been modified, are compressed into a compressed store prior to being written to a page file, after which the memory pages can be repurposed by a memory manager. The memory commit charge for the memory pages compressed into the compressed store is borrowed from the program process by a compressed storage manager, reducing the memory commit charge of the compressed storage manager. Subsequent requests from the memory manager for memory pages that have been compressed into a compressed store are satisfied by accessing the compressed store memory pages (including retrieving the compressed store memory pages from the page file if written to the page file), decompressing the requested memory pages, and returning the requested memory pages to the memory manager.