公开(公告)号：US06528432B1

公开(公告)日：2003-03-04

申请号：US09729455

申请日：2000-12-05

申请人： Minh Van Ngo ,  Dawn Hopper ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Dawn Hopper ,  Robert A. Huertas

IPC分类号： H01L214763

CPC分类号： H01L23/5329 ,  H01L21/31058 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/00

摘要： Degradation of organic low-k interlayer dielectrics during fabrication is substantially prevented or significantly reduced by treatment with a H2- or H2/N2-containing plasma. Embodiments include treating a SiCOH, such as Black Diamond®, ILD with an H2 or H2/N2 plasma after deposition, after forming a damascene opening therein and/or after CMP but prior to capping layer deposition.

摘要翻译： 通过用含H2或H2 / N2的等离子体处理，可以显着地防止或显着降低制造过程中有机低k层间电介质的退化。 实施方案包括在沉积之后，在其中形成镶嵌开口和/或CMP之后，但在覆盖层沉积之前，用H 2或H 2 / N 2等离子体处理SiCOH，例如Black Diamond，ILD。

公开(公告)号：US06383925B1

公开(公告)日：2002-05-07

申请号：US09497850

申请日：2000-02-04

申请人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

发明人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

摘要翻译： 通过在具有氨和氮气的等离子体的反应室中处理Cu或Cu合金互连构件的CMP暴露表面之后，通过将Cu或Cu合金互连构件的阻挡层或覆盖层的粘合性显着提高， 一段时间以减少表面氧化物，然后将硅烷引入反应室，以在氮气存在下在高密度等离子体条件下沉积阻挡层，例如氮化硅。 在等离子体氧化物层还原和等离子体阻挡层沉积期间氮的存在显着提高了阻挡层对Cu或Cu合金表面的粘附性。

公开(公告)号：US06221793B1

公开(公告)日：2001-04-24

申请号：US09517092

申请日：2000-03-01

申请人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Hartmut Ruelke ,  Robert A. Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

摘要： A process for super low deposition rate plasma enhanced chemical vapor deposition (PECVD) of undoped oxide on a single station deposition is provided. A very thin PECVD oxide layer used, for instance, as an oxide liner between a polysilicon gate and a nitride spacer, may be produced in a PECVD chamber with a reduced flow rate of silane, nitrous oxide and molecular nitrogen. The deposition rate may be lowered to 20 angstroms/minute, for example, with this long deposition time providing a better process control. At the same time, the film is dense, silicon rich, highly compressive, provides excellent step coverage and acceptable thickness uniformity.

摘要翻译： 提供了一种用于单站沉积的超低沉积速率等离子体增强化学气相沉积（PECVD）未掺杂氧化物的方法。 例如，可以在具有降低的硅烷，一氧化二氮和分子氮的流速的PECVD室中产生非常薄的PECVD氧化物层，例如，作为多晶硅栅极和氮化物间隔物之间​​的氧化物衬垫。 沉积速率可以降低到20埃/分钟，例如，这种长的沉积时间提供更好的工艺控制。 同时，薄膜致密，富硅，高压缩，提供优异的台阶覆盖和可接受的厚度均匀性。

公开(公告)号：US06818557B1

公开(公告)日：2004-11-16

申请号：US10317053

申请日：2002-12-12

申请人： Minh Van Ngo ,  Christine Hau-Riege ,  Steve Avanzino ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christine Hau-Riege ,  Steve Avanzino ,  Robert A. Huertas

IPC分类号： H01L2144

CPC分类号： H01L21/76883 ,  C23C16/0245 ,  C23C16/325 ,  H01L21/3148 ,  H01L21/32136 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, shutting off the power, discontinuing the N2 flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

摘要翻译： 封接的Cu或Cu合金互连的电迁移阻力得到显着改善，并且通过用含有NH 3和N 2的等离子体依次和连续地处理埋入的Cu的暴露的平坦化表面，显着地降低了小丘形成，加快引入三甲基硅烷，然后引发 沉积碳化硅盖层。 实施方案包括用用N 2稀释的软NH 3等离子体处理嵌入的Cu的暴露表面，切断电源，停止N 2流并引入He，然后在三个阶段升高引入三甲基硅烷，然后引发等离子体增强化学 同时在整个等离子体处理和碳化硅覆盖层沉积期间保持基本相同的335℃的温度。 实施例还包括形成在介电常数（k）小于3.9的介电材料中形成的Cu双镶嵌结构。

公开(公告)号：US06686232B1

公开(公告)日：2004-02-03

申请号：US10173717

申请日：2002-06-19

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper ,  Hieu Pham

IPC分类号： H01L21471

CPC分类号： H01L29/6659 ,  C23C16/345 ,  H01L21/3185 ,  H01L29/6656

摘要： A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.

摘要翻译： 通过减少NH 3流速和/或降低SiH 4流速，通过PECVD以超低沉积速率沉积薄的氮化硅层。 实施例包括在栅电极上的薄氧化硅衬垫上以100至800sccm的NH 3流速，50至100sccm的SiH 4流率和50至100sccm的SiH 4流速沉积例如100或更小的氮化硅薄层 0.8〜1.8乇减压。 本发明的实施例还包括在多个沉积阶段中沉积氮化硅层，例如，将氮化硅层沉积在各自的五个沉积阶段中。

公开(公告)号：US06627973B1

公开(公告)日：2003-09-30

申请号：US10244129

申请日：2002-09-13

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L29167

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06562416B2

公开(公告)日：2003-05-13

申请号：US09846187

申请日：2001-05-02

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Dawn Hopper

IPC分类号： C23C1402

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76807

摘要： Low resistant vias are formed by sequentially treating an opening in an interlayer dielectric and the exposed surface of a lower metal feature with an NH3 plasma followed by a N2/H2 plasma, thereby removing any oxide on the metal surface and removing residual polymers or polymeric deposits generated during etching to form the opening. Embodiments include forming a dual damascene opening in a low-k interlayer dielectric exposing the upper surface of a lower Cu or Cu alloy feature, sequentially treating the opening and the upper surface of the lower metal feature with an NH3 plasma and then with a N2/H2 plasma, Ar sputter etching, depositing a barrier layer lining the opening, depositing a seedlayer and filling the opening with Cu or a Cu alloy.

公开(公告)号：US06489253B1

公开(公告)日：2002-12-03

申请号：US09788045

申请日：2001-02-16

申请人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Robert A. Huertas ,  Lu You ,  King Wai Kelwin Ko ,  Pei-Yuan Gao

IPC分类号： H01L21469

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/31625 ,  H01L21/76801

摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.

摘要翻译： 一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。 本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全 消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。 在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。 此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

公开(公告)号：US06482755B1

公开(公告)日：2002-11-19

申请号：US09880513

申请日：2001-06-12

申请人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas

IPC分类号： H01L2131

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/76883

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed over the semiconductor substrate has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing lines the opening, and a copper or copper alloy conductor core fills the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. and above 3000 watts source power to reduce the residual oxide on the conductor core material. A silicon nitride capping layer is deposited by high density plasma (HDP) deposition with the source power between 2250 and 2750 watts and the bias power between 1800 and 2200 watts to suppress the formation of hillocks.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体衬底上方形成有形成在其中的开口的电介质层。 前述的钛，钽，钨或氮化物的阻挡层形成开口，铜或铜合金导体芯填充阻挡层上的通道开口。 在导体芯和阻挡层平坦化之后，进行氨，氮化氢或氢等离子体处理，其在低于300℃和高于3000瓦的源功率下进行，以减少导体芯材上的残余氧化物。 氮化硅覆盖层通过高功率等离子体（HDP）沉积沉积，源功率在2250和2750瓦之间，偏置功率在1800至2200瓦之间，以抑制形成小丘。

公开(公告)号：US06348410B1

公开(公告)日：2002-02-19

申请号：US09705396

申请日：2000-11-02

申请人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Dawn M. Hopper ,  Robert A. Huertas

IPC分类号： H01L2144

CPC分类号： H01L21/76883 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76834

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。 阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。 在导体芯和阻挡层平坦化之后，在300℃下进行等离子体处理以减少导体芯材料。 盖层的一部分在300℃下沉积，剩余部分在400℃下沉积