Method of subdividing a wafer
    11.
    发明授权
    Method of subdividing a wafer 有权
    细分晶圆的方法

    公开(公告)号:US06756288B1

    公开(公告)日:2004-06-29

    申请号:US10019138

    申请日:2002-06-03

    IPC分类号: H01L21301

    摘要: In a method of dicing a wafer, which comprises a plurality of individual circuit structures, a trench is first defined between at least two circuit structures on one face of the wafer. Subsequently, the trench is deepened down to a defined depth. Following this, one face of the wafer has fixed thereto a re-detachable intermediate support composed of a fixed intermediate support substrate and an adhesive medium which is applied to said intermediate support substrate and which can specifically be modified in terms of its adhesive strength, whereupon the wafer is dry-etched from the opposite face so that circuit chips are obtained which are connected to one another only via the intermediate support. Subsequently, the circuit chips are removed from the intermediate support. This method substantially reduces mechanical impairments that may occur during dicing of the circuit chips; on the one hand, this permits the production of circuit chips with a thickness of less than 50 &mgr;m and, on the other hand, it leads to mechanically substantially undamaged circuit chips.

    摘要翻译: 在包括多个单独电路结构的晶片切割的方法中,首先在晶片的一个面上的至少两个电路结构之间限定沟槽。 随后,将沟槽加深到限定的深度。 此后,晶片的一个面固定有由固定的中间支撑基板和粘合剂介质组成的可再拆卸的中间支撑件,该中间支撑件施加到所述中间支撑基板上,并且可以根据其粘合强度具体地进行修改, 从相对面干蚀刻晶片,从而获得仅通过中间支撑件相互连接的电路芯片。 随后,将电路芯片从中间支撑件移除。 该方法基本上减少了在电路芯片切割期间可能发生的机械损伤; 一方面,这允许生产厚度小于50um的电路芯片,另一方面它导致机械上基本上未损坏的电路芯片。

    Method for vertically integrating active circuit planes and vertically integrated circuit produced using said method
    12.
    发明授权
    Method for vertically integrating active circuit planes and vertically integrated circuit produced using said method 有权
    用于使用所述方法产生的垂直积分有源电路平面和垂直集成电路的方法

    公开(公告)号:US06444493B1

    公开(公告)日:2002-09-03

    申请号:US09857373

    申请日:2001-09-21

    IPC分类号: H01L2144

    摘要: In a method for vertically integrating active circuit planes, a first substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as outer connecting areas on the first main surface is provided in a first step. A second substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as open or openable areas on the first main surface is provided. The first main surfaces of the first and second substrates are joined in such a way that the connecting areas of the first substrate are connected to those of the second substrate in an electrically conductive manner in such a way that the outer connecting areas of the first substrate are in alignment with the open or openable areas of the second substrate. Subsequently, the second substrate is thinned and the outer connecting areas are exposed through the open or openable areas. The resultant chips can be further processed making use of standard methods.

    摘要翻译: 在用于垂直积分有源电路平面的方法中,在其第一主表面中具有至少一个集成电路并且还具有集成电路的连接区域以及第一主表面上的外连接区域的第一基板设置在第一 步。 第二基板在其第一主表面中具有至少一个集成电路,并且还具有用于集成电路的连接区域以及第一主表面上的打开或可打开区域。 第一和第二基板的第一主表面以这样的方式接合,使得第一基板的连接区域以导电方式连接到第二基板的连接区域,使得第一基板的外部连接区域 与第二基板的打开或可打开的区域对齐。 随后,第二基板变薄并且外部连接区域通过打开或可打开的区域露出。 所得到的芯片可以使用标准方法进一步加工。

    Method for contacting a circuit chip
    13.
    发明授权
    Method for contacting a circuit chip 有权
    接触电路芯片的方法

    公开(公告)号:US06365440B1

    公开(公告)日:2002-04-02

    申请号:US09786132

    申请日:2001-07-16

    申请人: Michael Feil

    发明人: Michael Feil

    IPC分类号: H01L2144

    摘要: In a method for contacting a circuit chip containing an integrated circuit of a thickness less than 50 &mgr;m, which has at least two pads on a first main surface, the circuit chip is first of all placed onto a main surface of a support substrate with a second main surface which faces this first main surface, in such a way that the entire thickness of the circuit chip protrudes from the surface of the support substrate. A structured metallic coating is then applied to the first main surface of the circuit chip and the surface of the support substrate by means of screen printing or stamping, in order to connect the pads of the circuit chip to a conductor structure located on the main surface of the support substrate. Alternatively, the screen printing or stamping process is used to apply a structured metallic coating to the first main surface of the circuit chip and the surface of the support substrate, in order to produce a peripheral conductor structure, which is connected to the pads of the circuit chip, on the main surface of the support substrate and on the first main surface of the circuit chip.

    摘要翻译: 在包含厚度小于50um的集成电路的电路芯片的接触方法中,该电路芯片在第一主表面上具有至少两个焊盘,首先将电路芯片放置在支撑衬底的主表面上,其中 第二主表面面对该第一主表面,使得电路芯片的整个厚度从支撑基板的表面突出。 然后通过丝网印刷或冲压将结构化金属涂层施加到电路芯片的第一主表面和支撑基板的表面,以便将电路芯片的焊盘连接到位于主表面上的导体结构 的支撑基板。 或者,使用丝网印刷或冲压工艺将结构化金属涂层施加到电路芯片的第一主表面和支撑基板的表面,以便产生外围导体结构,该外围导体结构连接到 电路芯片,在支撑基板的主表面和电路芯片的第一主表面上。