公开(公告)号：US20240365623A1

公开(公告)日：2024-10-31

申请号：US18764775

申请日：2024-07-05

Applicant: InnoLux Corporation

Inventor： Shun-Yuan HU ,  Chin-Lung TING ,  Li-Wei MAO ,  Ming-Chun TSENG ,  Kung-Chen KUO ,  Yi-Hua HSU ,  Ker-Yih KAO

IPC: H10K59/18 ,  G09F9/302 ,  G09G3/00 ,  H01L21/66 ,  H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H10K50/86 ,  H10K59/131 ,  H10K77/10

CPC classification number: H10K59/18 ,  G09F9/3026 ,  G09G3/006 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/162 ,  H01L25/167 ,  H01L27/124 ,  H10K50/865 ,  H10K59/131 ,  H10K77/111 ,  H01L22/14 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A light-emitting device is provided. The light-emitting device includes a circuit substrate, an array substrate, a plurality of light-emitting units and a driver. The circuit substrate has a top surface. A top circuit is disposed on the top surface. The array substrate is disposed on the top surface of the circuit substrate and electrically connected to the top circuit. The light-emitting units are disposed on the array substrate. The light-emitting device further includes an electrical connection structure, a plurality of light extraction layers, a protective layer, a plurality of test pads, and a light absorption layer. The plurality of test pads are disposed on the array substrate, and the light absorption layer covers at least one of the test pads.

公开(公告)号：US12040281B2

公开(公告)日：2024-07-16

申请号：US17401330

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Yuan Chang ,  Jiun-Yi Wu ,  Jeng-Shien Hsieh ,  Tin-Hao Kuo

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/24226 ,  H01L2224/82005 ,  H01L2924/3511

Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

公开(公告)号：US20240195047A1

公开(公告)日：2024-06-13

申请号：US18519181

申请日：2023-11-27

Applicant: Phoenix Pioneer Technology Co., Ltd.

Inventor： Che-Wei Hsu ,  Shih-Ping Hsu

IPC: H01Q1/22 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01Q1/38

CPC classification number: H01Q1/2283 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/24 ,  H01L24/82 ,  H01Q1/38 ,  H01L2224/24226 ,  H01L2224/82005

Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.

公开(公告)号：US20240170433A1

公开(公告)日：2024-05-23

申请号：US18283721

申请日：2021-03-25

Applicant: LG ELECTRONICS INC.

Inventor： Bongseok CHOI ,  Joonkwon MOON ,  Sungjin PARK ,  Taesu OH

IPC: H01L23/00 ,  H01L25/075 ,  H01L25/13 ,  H01L33/62

CPC classification number: H01L24/24 ,  H01L24/25 ,  H01L25/0753 ,  H01L25/13 ,  H01L33/62 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2512 ,  H01L2924/12041

Abstract: A light emitting device package include a first layer; a plurality of light emitting devices on the first layer; a plurality of electrode pads surrounding the plurality of light emitting devices; a second layer on the plurality of light emitting devices; a plurality of connection electrodes disposed on the second layer to connect between the plurality of light emitting devices and the plurality of electrode pads, and a third layer on the plurality of connection electrodes.

公开(公告)号：US11967563B2

公开(公告)日：2024-04-23

申请号：US17402734

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/562 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US11841531B2

公开(公告)日：2023-12-12

申请号：US17815962

申请日：2022-07-29

Applicant: The Research Foundation for The State University of New York

Inventor： Douglas Coolbaugh ,  Douglas La Tulipe ,  Gerald Leake

IPC: G02B6/12 ,  H01L21/48 ,  H01L23/498 ,  H01L31/02 ,  H01L31/0232 ,  G02B6/13 ,  G02B6/42 ,  H01L23/00 ,  G02B6/43 ,  H01L27/12 ,  H01L21/18 ,  H01L21/762 ,  H01L25/18 ,  H01L25/00 ,  H01L25/065

CPC classification number: G02B6/12002 ,  G02B6/131 ,  G02B6/4232 ,  G02B6/43 ,  H01L21/187 ,  H01L21/486 ,  H01L23/49838 ,  H01L24/92 ,  H01L27/1266 ,  H01L31/02002 ,  H01L31/02016 ,  H01L31/02327 ,  G02B6/12 ,  G02B6/12004 ,  G02B2006/121 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12138 ,  G02B2006/12147 ,  G02B2006/12176 ,  G02B2006/12178 ,  H01L21/7624 ,  H01L21/76224 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/80 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1203 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05582 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/16145 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/8203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/9202 ,  H01L2224/82 ,  H01L2224/9202 ,  H01L2224/03 ,  H01L2224/9222 ,  H01L2224/80001 ,  H01L2224/81

Abstract: There is set forth herein an optoelectrical device, comprising: a substrate; an interposer dielectric stack formed on the substrate, the interposer dielectric stack including a base interposer dielectric stack, a photonics device dielectric stack, and a bond layer that integrally bonds the photonics device dielectric stack to the base interposer dielectric stack. There is set forth herein a method comprising building an interposer base structure on a first wafer having a first substrate, including fabricating a plurality of through vias in the first substrate and fabricating within an interposer base dielectric stack formed on the first substrate one or more metallization layers; and building a photonics structure on a second wafer having a second substrate, including fabricating one or more photonics devices within a photonics device dielectric stack formed on the second substrate.

公开(公告)号：US20230317673A1

公开(公告)日：2023-10-05

申请号：US17710941

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Vivek Swaminathan Sridharan ,  Rajen Manicon Murugan ,  Patrick Francis Thompson

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L24/24 ,  H01L24/16 ,  H01L24/20 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/73209 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2924/37001 ,  H01L2924/186 ,  H01L2924/182 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/17134

Abstract: A described example includes: a reconstituted semiconductor device flip chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die mounted in a dielectric layer and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.

公开(公告)号：US20230253380A1

公开(公告)日：2023-08-10

申请号：US17669252

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Suresh RAMALINGAM ,  Hong SHI

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/24 ,  H01L2224/24265 ,  H01L2924/19103 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2224/244 ,  H01L2224/24226

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

公开(公告)号：US11676928B2

公开(公告)日：2023-06-13

申请号：US17396346

申请日：2021-08-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Romain Coffy ,  Patrick Laurent ,  Laurent Schwartz

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L21/56 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/16 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/0233 ,  H01L2224/02315 ,  H01L2224/02381 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82048 ,  H01L2224/82108

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

公开(公告)号：US20230154822A1

公开(公告)日：2023-05-18

申请号：US17922944

申请日：2020-05-20

Applicant: Nippon Telegraph and Telephone Corporation

Inventor： Yusuke Araki ,  Hideaki Matsuzaki ,  Yuta Shiratori

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L25/0655 ,  H01L24/73 ,  H01L24/16 ,  H01L24/24 ,  H01L21/565 ,  H01L21/568 ,  H01L21/4882 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2224/73209 ,  H01L2224/24226 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/1611 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1011

Abstract: A semiconductor device includes a first heat sink formed in contact with a back surface of a first semiconductor chip, and a second heat sink formed in contact with a back surface of a second semiconductor chip. The first heat sink is made of a material with larger thermal conductivity than that of the first semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside. The second heat sink is made of a material with larger thermal conductivity than that of the second semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside.