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公开(公告)号:US20180301395A1
公开(公告)日:2018-10-18
申请号:US16016329
申请日:2018-06-22
发明人: Haruki Ito , Nobuaki Hashimoto
IPC分类号: H01L23/48 , H03H9/10 , H01L23/482 , H03H9/05 , H01L23/50 , H01L23/522 , H01L23/00
CPC分类号: H01L23/481 , H01L23/4824 , H01L23/50 , H01L23/522 , H01L24/12 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05025 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/05686 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H03H9/0547 , H03H9/0552 , H03H9/1071 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01074 , H01L2924/01023
摘要: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
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公开(公告)号:US20180301393A1
公开(公告)日:2018-10-18
申请号:US16016285
申请日:2018-06-22
发明人: Haruki Ito , Nobuaki Hashimoto
IPC分类号: H01L23/48 , H03H9/10 , H01L23/482 , H03H9/05 , H01L23/50 , H01L23/522 , H01L23/00
CPC分类号: H01L23/481 , H01L23/4824 , H01L23/50 , H01L23/522 , H01L24/12 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05025 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/05686 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H03H9/0547 , H03H9/0552 , H03H9/1071 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01074 , H01L2924/01023
摘要: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
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公开(公告)号:US10037956B2
公开(公告)日:2018-07-31
申请号:US14596851
申请日:2015-01-14
申请人: Intel Corporation
发明人: Madhav Datta , Dave Emory , Subhash M. Joshi , Susanne Menezes , Doowon Suh
IPC分类号: H01L23/488 , H01L23/00 , H01L23/498
CPC分类号: H01L24/11 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/11009 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/11901 , H01L2224/11912 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13166 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.
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公开(公告)号:US10020245B2
公开(公告)日:2018-07-10
申请号:US14150795
申请日:2014-01-09
发明人: Henrik Ewe , Joachim Mahler , Anton Prueckl , Stefan Landau
IPC分类号: H01L23/48 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/18 , H05K1/18 , H01L21/56 , H01L21/683 , H01L23/31 , H05K1/05 , H05K3/46
CPC分类号: H01L23/481 , H01L21/56 , H01L21/6835 , H01L23/3107 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2221/68372 , H01L2221/68377 , H01L2224/0557 , H01L2224/24137 , H01L2224/2518 , H01L2224/32245 , H01L2224/73267 , H01L2224/76155 , H01L2224/82039 , H01L2224/82102 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01068 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15192 , H01L2924/15787 , H01L2924/19041 , H01L2924/19105 , H05K1/05 , H05K1/185 , H05K1/188 , H05K3/4644 , H05K2201/09745 , H05K2201/09972 , H05K2203/0353 , H05K2203/1469 , H01L2924/00 , H01L2224/05552
摘要: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.
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公开(公告)号:US10011098B2
公开(公告)日:2018-07-03
申请号:US14856967
申请日:2015-09-17
发明人: Roy R. Yu , Wilfried Haensch
IPC分类号: H01L23/498 , H01L25/00 , H01L25/065 , B32B37/02 , H01L23/473 , H01L23/00 , H01L25/18 , H01L23/48 , B32B37/12 , B32B38/18 , H01L29/06
CPC分类号: B32B37/02 , B32B37/12 , B32B38/1841 , B32B2309/105 , B32B2310/0843 , B32B2457/14 , H01L23/473 , H01L23/481 , H01L23/49827 , H01L24/09 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/0401 , H01L2224/05144 , H01L2224/05147 , H01L2224/06181 , H01L2224/08145 , H01L2224/13147 , H01L2224/16147 , H01L2224/26135 , H01L2224/291 , H01L2224/29147 , H01L2224/2919 , H01L2224/32145 , H01L2224/73253 , H01L2224/81191 , H01L2224/83005 , H01L2224/8314 , H01L2224/83141 , H01L2224/9202 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1032 , H01L2924/10329 , H01L2924/1204 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15153 , H01L2224/83 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00
摘要: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.
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公开(公告)号:US20180130751A1
公开(公告)日:2018-05-10
申请号:US15863164
申请日:2018-01-05
申请人: X-Celeprint Limited
发明人: Christopher Bower
IPC分类号: H01L23/538 , H01L21/683 , H01L23/00 , H01L21/66
CPC分类号: H01L23/5389 , H01L21/6835 , H01L22/32 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/83 , H01L2221/68368 , H01L2221/68372 , H01L2224/21 , H01L2224/2101 , H01L2224/2105 , H01L2224/211 , H01L2224/214 , H01L2224/24011 , H01L2224/2405 , H01L2224/24101 , H01L2224/24137 , H01L2224/244 , H01L2224/76155 , H01L2224/82102 , H01L2224/82106 , H01L2224/95001 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/15788 , H01L2924/00 , H01L2224/83
摘要: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.
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公开(公告)号:US09950154B2
公开(公告)日:2018-04-24
申请号:US15713291
申请日:2017-09-22
申请人: Stryker Corporation
发明人: Robert Brindley , John Janik , Edward Chia-Ning Tang , James Bernard Dunlop , Joseph Leland Spangler
CPC分类号: A61N1/05 , A61N1/0553 , A61N1/08 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/2101 , H01L2224/211 , H01L2224/215 , H01L2224/221 , H01L2224/24227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H05K1/118 , H05K1/185 , H01L2924/00
摘要: A method of forming an implantable electrode array that includes one or more packaged control modules. A control module is packaged by mounting the module to a substrate and forming a containment ring around the module. A conformal coating is disposed over the surface of the module to cover the carrier. Within the containment ring, the conformal coating hardens to form a non-porous shell around the control module. The one or more packaged control modules are placed in a flexible array. Electrodes that are mounted to or embedded in the flexible carrier are connected to the one or more control modules.
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公开(公告)号:US20180068982A1
公开(公告)日:2018-03-08
申请号:US15800127
申请日:2017-11-01
发明人: Alexander Heinrich
IPC分类号: H01L25/065 , H01L21/683
CPC分类号: H01L25/0655 , H01L21/6835 , H01L23/13 , H01L23/4827 , H01L23/49503 , H01L23/49513 , H01L23/544 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/83 , H01L24/97 , H01L25/50 , H01L2221/68354 , H01L2223/54426 , H01L2223/54486 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/05687 , H01L2224/06183 , H01L2224/26145 , H01L2224/26175 , H01L2224/27334 , H01L2224/27436 , H01L2224/2908 , H01L2224/291 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/2916 , H01L2224/29166 , H01L2224/29171 , H01L2224/2919 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/75102 , H01L2224/75251 , H01L2224/75265 , H01L2224/75303 , H01L2224/75753 , H01L2224/7598 , H01L2224/83002 , H01L2224/83005 , H01L2224/83007 , H01L2224/83024 , H01L2224/83055 , H01L2224/83065 , H01L2224/83075 , H01L2224/8309 , H01L2224/83091 , H01L2224/83092 , H01L2224/83101 , H01L2224/83127 , H01L2224/83132 , H01L2224/83143 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83201 , H01L2224/83203 , H01L2224/83208 , H01L2224/83222 , H01L2224/83385 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83466 , H01L2224/83469 , H01L2224/8381 , H01L2224/83815 , H01L2224/8382 , H01L2224/83825 , H01L2224/8384 , H01L2224/83851 , H01L2224/83855 , H01L2224/83856 , H01L2224/83862 , H01L2224/83907 , H01L2224/83986 , H01L2224/97 , H01L2924/00012 , H01L2924/01015 , H01L2924/04941 , H01L2924/0496 , H01L2924/15153 , H01L2924/15156 , H01L2924/15157 , H01L2924/157 , H01L2924/15747 , H01L2924/1576 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/01047 , H01L2924/01028 , H01L2924/01026 , H01L2924/0105 , H01L2924/01082 , H01L2924/01074 , H01L2924/01024 , H01L2924/01023 , H01L2924/01027
摘要: A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.
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公开(公告)号:US09905497B2
公开(公告)日:2018-02-27
申请号:US14844427
申请日:2015-09-03
发明人: Takeshi Susaki , Masahito Shindo , Kazumi Onda
IPC分类号: H01L23/495 , B23K20/00 , B23K20/10 , H01L21/56 , H01L23/00 , H01L21/82 , H01L21/48 , H01L23/31 , H01L25/065 , B23K101/42
CPC分类号: H01L23/49541 , B23K20/005 , B23K20/106 , B23K2101/42 , H01L21/4842 , H01L21/565 , H01L21/82 , H01L23/3107 , H01L23/49503 , H01L23/49575 , H01L23/49589 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/0655 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/0603 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/484 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/85099 , H01L2224/85203 , H01L2224/85205 , H01L2224/85399 , H01L2924/00014 , H01L2924/00015 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2224/78 , H01L2924/00 , H01L2224/48824 , H01L2924/00012
摘要: The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc.
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公开(公告)号:US09883587B2
公开(公告)日:2018-01-30
申请号:US15084530
申请日:2016-03-30
申请人: Petteri Palm , Risto Tuominen , Antti Iihola
发明人: Petteri Palm , Risto Tuominen , Antti Iihola
IPC分类号: H05K1/09 , H01L23/498 , H01L23/538 , H01L23/00 , H05K1/18 , H01L21/48 , H05K3/30
CPC分类号: H05K1/09 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49838 , H01L23/49866 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13144 , H01L2224/13147 , H01L2224/24137 , H01L2224/24227 , H01L2224/32245 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15153 , H01L2924/1517 , H01L2924/351 , H05K1/182 , H05K1/188 , H05K3/305 , H05K2201/0355 , H05K2201/09509 , H05K2201/0969 , H05K2201/10674 , H05K2203/063 , Y10T29/49117 , Y10T29/4913 , H01L2924/00
摘要: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.
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