公开(公告)号：US06414362B1

公开(公告)日：2002-07-02

申请号：US09879467

申请日：2001-06-12

申请人： Frank Kuo ,  Mohammed Kasem ,  Sen Mao ,  Oscar Ou ,  Sam Kuo

发明人： Frank Kuo ,  Mohammed Kasem ,  Sen Mao ,  Oscar Ou ,  Sam Kuo

IPC分类号： H01L31113

CPC分类号： H01L24/40 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49827 ,  H01L24/36 ,  H01L2224/40245 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2924/01006 ,  H01L2924/01047

摘要： A power semiconductor device includes a die having a drain contact, a source contact, a primary gate contact, a partitioning region that partitions the source contact, and a secondary gate contact disposed in the partitioning region. A conductive strip is connected to the primary and secondary gate contacts. An insulation layer encloses a segment of the conductive strip. A conductive connecting member includes a metal sheet and a conductive paste. The metal sheet is attached to the source contact via the conductive paste and is formed with a groove to expose the insulation layer from the metal sheet.

摘要翻译： 功率半导体器件包括具有漏极接触，源极接触，主栅极接触，分隔源极接触的分隔区域和设置在分隔区域中的次级栅极接触的管芯。 导电条连接到初级和次级栅极触点。 绝缘层包围导电条的一段。 导电连接构件包括金属片和导电膏。 金属片经由导电膏附接到源极接触，并且形成有凹槽以使绝缘层与金属片露出。

公开(公告)号：US06744119B2

公开(公告)日：2004-06-01

申请号：US09978603

申请日：2001-10-15

申请人： Frank Kuo ,  Sen Mao ,  Sam Kuo ,  Oscar Ou

发明人： Frank Kuo ,  Sen Mao ,  Sam Kuo ,  Oscar Ou

IPC分类号： H01L23495

CPC分类号： H01L23/49503 ,  H01L24/32 ,  H01L2924/10158

摘要： A die pad (81) of a leadframe (8) has a plurality of slots (811-814) that extend through the die pad to define a restrictive region (815). One of the slots extends around a comer of the restrictive region outside where a die (7) is connected to the die pad by solder paste (6). Because of the cohesion of the solder paste, the solder paste does not flow into the slots. The solder paste is thereby restricted to the restrictive region. This prevents the die from drifting or rotating so as to increase the packaging quality.

摘要翻译： 引线框架（8）的管芯焊盘（81）具有延伸穿过管芯焊盘以限定限制区域（815）的多个槽（811-814）。 其中一个槽围绕限制区域的一个角延伸，其中管芯（7）通过焊膏（6）连接到管芯焊盘。 由于焊膏的凝聚性，焊膏不会流入槽内。 因此，焊膏被限制在限制区域。 这样可防止模具漂移或旋转，从而提高包装质量。

公开(公告)号：US20110175217A1

公开(公告)日：2011-07-21

申请号：US12730230

申请日：2010-03-24

申请人： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

发明人： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

摘要翻译： 本技术涉及通过将多个管芯电耦合到上引线框架和下引线框架而封装的半导体。 上引线框架中的每个相应引线组的相对边缘弯曲。 上引线框架中的引线电耦合在相应管芯上的相应触头和下引线框架中引线的相应下部。 上引线框架的每个相应的引线组的弯曲的相对边缘在封装之前支撑上引线框架，以在封装半导体中实现上引脚和下引线框架的引线之间的多个管芯的期望位置。 在封装的芯片被分离之后，上部引线具有L形并且在芯片的上侧上电耦合管芯触头，以在芯片的下侧引出引线，使得封装触点位于半导体封装的同一侧。

公开(公告)号：US08586419B2

公开(公告)日：2013-11-19

申请号：US12730230

申请日：2010-03-24

申请人： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

发明人： Serge Jaunay ,  Suresh Belani ,  Frank Kuo ,  Sen Mao ,  Peter Wang

IPC分类号： H01L21/00

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

摘要翻译： 本技术涉及通过将多个管芯电耦合到上引线框架和下引线框架而封装的半导体。 上引线框架中的每个相应引线组的相对边缘弯曲。 上引线框架中的引线电耦合在相应管芯上的相应触头和下引线框架中引线的相应下部。 上引线框架的每个相应的引线组的弯曲的相对边缘在封装之前支撑上引线框架，以在封装半导体中实现上引脚和下引线框架的引线之间的多个管芯的期望位置。 在封装的芯片被分离之后，上部引线具有L形并且在芯片的上侧上电耦合管芯触头，以在芯片的下侧引出引线，使得封装触点位于半导体封装的同一侧。

公开(公告)号：USD472528S1

公开(公告)日：2003-04-01

申请号：US29151069

申请日：2001-10-31

申请人： Yehja Mohammed Kasem ,  Frank Kuo ,  Eddy Tjhia

设计人： Yehja Mohammed Kasem ,  Frank Kuo ,  Eddy Tjhia

CPC分类号： H01L2924/181 ,  H01L2924/00012

公开(公告)号：USD466873S1

公开(公告)日：2002-12-10

申请号：US29151024

申请日：2001-10-31

申请人： Yehja Mohammed Kasem ,  Frank Kuo ,  Eddy Tjhia

设计人： Yehja Mohammed Kasem ,  Frank Kuo ,  Eddy Tjhia

公开(公告)号：US20140370661A1

公开(公告)日：2014-12-18

申请号：US14474420

申请日：2014-09-02

申请人： Frank Kuo ,  Suresh Belani

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

摘要翻译： 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US09184152B2

公开(公告)日：2015-11-10

申请号：US14341772

申请日：2014-07-26

申请人： Frank Kuo ,  Suresh Belani

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L29/72 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

摘要翻译： 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US08822273B2

公开(公告)日：2014-09-02

申请号：US13229667

申请日：2011-09-09

申请人： Frank Kuo ,  Suresh Belani

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L29/72

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

摘要翻译： 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US20120112331A1

公开(公告)日：2012-05-10

申请号：US13229667

申请日：2011-09-09

申请人： Frank Kuo ,  Suresh Belani

发明人： Frank Kuo ,  Suresh Belani

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

摘要翻译： 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。