公开(公告)号：US20230360857A1

公开(公告)日：2023-11-09

申请号：US18222513

申请日：2023-07-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/2325

Abstract: A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrodes each at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface in a lamination direction of the capacitor main body, and opposed and spaced apart from each other in a length direction connecting the two end surfaces. The two interposers each include a first recess portion on an end surface of the interposer opposed to an end surface facing the other interposer, in an area around a middle portion of the interposer in a width direction, and second recess portions on both sides in the width direction of the first recess portion, and each having a thickness of about ±10% of a half of a thickness of the interposer.

公开(公告)号：US20230245831A1

公开(公告)日：2023-08-03

申请号：US18133570

申请日：2023-04-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G4/12 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012 ,  H01G4/2325

Abstract: A method of manufacturing a multilayer ceramic capacitor includes alternately laminating dielectric layers and internal electrode layers to manufacture a multilayer body, forming an external electrode connected with the internal electrode layers on each of two end surfaces of the multilayer body to manufacture a capacitor main body, connecting two interposers via a plate-shaped member, connecting the two interposers and the external electrode, and removing the plate-shape member.

公开(公告)号：US20220384099A1

公开(公告)日：2022-12-01

申请号：US17752900

申请日：2022-05-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G2/06 ,  H01G4/30 ,  H01G4/248 ,  H01G4/232 ,  H01G4/12 ,  H01G4/008

Abstract: An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes at a pair of multilayer body end surfaces of the multilayer body and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surfaces and the board side surfaces. One of the board main surfaces is located in a vicinity of the electronic element and joined with one of the multilayer body main surfaces in a vicinity of the interposer board. The interposer board is an alumina board. A mark portion is provided on one of the board main surfaces.

公开(公告)号：US20220301780A1

公开(公告)日：2022-09-22

申请号：US17489884

申请日：2021-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/008 ,  H01G4/012 ,  H01G2/06

Abstract: A method of manufacturing a multilayer ceramic capacitor includes alternately laminating dielectric layers and internal electrode layers to manufacture a multilayer body, forming an external electrode connected with the internal electrode layers on each of two end surfaces of the multilayer body to manufacture a capacitor main body, connecting two interposers via an insulator, holding the two interposers connected via the insulator on a holding portion, placing the capacitor main body on the two interposers on the holding portion such that the external electrode is connected to each of the two interposers, and removing the holding portion.

公开(公告)号：US20200312568A1

公开(公告)日：2020-10-01

申请号：US16822069

申请日：2020-03-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toshihiro HARADA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second internal electrode layers laminated in a lamination direction, and first and second external electrode connected to the internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The side margin including an inner layer and an outer layer. In a cross section including a lamination direction and a width direction obtained by cutting the laminate at a central portion in a length direction, Si is segregated in an inner region including the inner layer and a boundary between the inner layer and the central layer portion, and a Si segregation spot in the inner region has a larger area than a Si segregation spot in the outer layer.

公开(公告)号：US20170110248A1

公开(公告)日：2017-04-20

申请号：US15393346

申请日：2016-12-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Sui UNO ,  Takashi SAWADA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/232

Abstract: In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction.

公开(公告)号：US20160049249A1

公开(公告)日：2016-02-18

申请号：US14813280

申请日：2015-07-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yohei MUKOBATA ,  Takashi SAWADA ,  Sui UNO

IPC: H01G4/242 ,  H01G4/30 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

Abstract: In a multilayer capacitor, both a dimension in a thickness direction of a first terminal electrode on the first end surface and a dimension in the thickness direction of a second terminal electrode on the second end surface are greater than a minimum distance in the thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface.

Abstract translation: 在层叠电容器中，第一端面上的第一端子电极的厚度方向上的尺寸和第二端面上的第二端子电极的厚度方向的尺寸都大于第二端子板的厚度方向上的最小距离 第一内部电极和第二主表面的第一有效部分和在第二内部电极的第二有效部分和第二主表面之间的厚度方向上的最小距离。

公开(公告)号：US20240312723A1

公开(公告)日：2024-09-19

申请号：US18673499

申请日：2024-05-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/2325

Abstract: A method of manufacturing a multilayer ceramic capacitor includes alternately laminating dielectric layers and internal electrode layers to manufacture a multilayer body, forming an external electrode connected with the internal electrode layers on each of two end surfaces of the multilayer body to manufacture a capacitor main body, connecting two interposers via a plate-shaped member, connecting the two interposers and the external electrode, and removing the plate-shape member.

公开(公告)号：US20240186065A1

公开(公告)日：2024-06-06

申请号：US18442330

申请日：2024-02-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G2/06 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G2/065 ,  H01G4/008 ,  H01G4/2325 ,  H01G4/30 ,  H01G2/06 ,  H01G4/1227 ,  H01G4/232

Abstract: An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes at multilayer body end surfaces of the multilayer body and connected to internal electrode layers. One of the board main surfaces is in a vicinity of the electronic element and joined with a multilayer body main surface in a vicinity of the interposer board. The interposer board is an alumina board. At least one notch is in end regions including a board end surface, a board side surface in a vicinity thereof, a board main surface in a vicinity thereof, ridge portions between the board end surface and the board side surface, between the board end surface and the board main surface, and between the board side surface and the board main surface, and a corner portion between the board end surface, the board side surface, and the board main surface.

公开(公告)号：US20240136122A1

公开(公告)日：2024-04-25

申请号：US18400401

申请日：2023-12-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi YOKOMIZO ,  Shinobu CHIKUMA ,  Yohei MUKOBATA

IPC: H01G2/06 ,  H01G4/232 ,  H01G4/30

CPC classification number: H01G2/06 ,  H01G4/2325 ,  H01G4/30 ,  H01G4/008

Abstract: An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes each at a respective one of multilayer body end surfaces of the multilayer body and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surface and the board side surface. One of the board main surfaces is located in a vicinity of the electronic element and joined with one of multilayer body main surfaces in a vicinity of the interposer board. The interposer board is an alumina board. The external electrodes each include a first Sn plated layer that covers an outer surface of the interposer board in a vicinity of at least one board end surface.