公开(公告)号：US08797201B2

公开(公告)日：2014-08-05

申请号：US13925849

申请日：2013-06-25

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: H03M1/66

CPC classification number: H03M1/06 ,  G09G3/20 ,  G09G2300/0421 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2320/0276 ,  H03M1/66 ,  H03M1/765

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract translation: 驱动电路包括多个参考电压线和数模转换器。 参考电压线被配置为分别传输不同的灰度参考电压，其中灰度参考电压被划分为至少两组，并且第一个参考电压的参考电压线中的至少一个参考电压线的线径/线宽 所述至少两组中的电压组与所述至少两组中的第二电压组的参考电压线的线径/线宽不同。 数模转换器耦合到参考电压线以接收灰度参考电压，并且用于根据灰度参考电压将数字信号转换成灰度级电压。

公开(公告)号：US20130241631A1

公开(公告)日：2013-09-19

申请号：US13717648

申请日：2012-12-17

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Ju-Lin Huang ,  Keko-Chun Liang ,  Chun-Yung Cho ,  Cheng-Hung Chen

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F3/205

Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

Abstract translation: 输出级电路包括：第一晶体管，包括耦合到第一节点的第一端子，耦合到输出端子的第二端子，耦合到用于接收输入电压的输入端子的第三端子，以及耦合到第一端子的第四端子 用于接收第一电压的第一电源端子; 第二晶体管，包括耦合到第二节点的第一端子，耦合到输出端子的第二端子，耦合到输入端子用于接收输入电压的第三端子和耦合到地的第四端子; 以及耦合到输出端子以提供恒定电流的电流源。

公开(公告)号：US11069586B2

公开(公告)日：2021-07-20

申请号：US14968929

申请日：2015-12-15

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Chun-Yung Cho ,  Po-Yu Tseng

IPC: H01L23/495 ,  H01L21/66 ,  H01L23/498

Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.

公开(公告)号：US20170092572A1

公开(公告)日：2017-03-30

申请号：US14968929

申请日：2015-12-15

Applicant: Novatek Microelectronics Corp.

Inventor： Jhih-Siou Cheng ,  Chun-Yung Cho ,  Po-Yu Tseng

IPC: H01L23/495 ,  H01L21/66

CPC classification number: H01L22/32 ,  H01L23/49838 ,  H01L23/4985

Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.

公开(公告)号：US09270112B2

公开(公告)日：2016-02-23

申请号：US13865210

申请日：2013-04-18

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Che-Lun Hsu ,  Jhih-Siou Cheng ,  Chun-Yung Cho

IPC: H02H9/02 ,  H02H9/04 ,  G09G3/20

CPC classification number: H02H9/046 ,  G09G3/20 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  G09G2330/04 ,  G09G2330/06 ,  H03M1/00 ,  H03M1/0827 ,  H03M1/808

Abstract: A driving circuit includes several first electrostatic current limiting resistors and several digital to analog converter (DAC) units. First ends of these first electrostatic current limiting resistors common coupled to a global path to receive a reference voltage. These DAC units respectively coupled to second ends of the first electrostatic current limiting resistors one-on-one to receive the reference voltage through the first electrostatic current limiting resistors.

Abstract translation: 驱动电路包括几个第一静电电流限制电阻器和几个数模转换器（DAC）单元。 这些第一静电电流限制电阻的第一端公共耦合到全局路径以接收参考电压。 这些DAC单元分别耦合到第一静电电流限制电阻器的第二端，以通过第一静电电流限制电阻器接收参考电压。

公开(公告)号：US20150339960A1

公开(公告)日：2015-11-26

申请号：US14645434

申请日：2015-03-12

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chia-En Wu

IPC: G09G3/00

CPC classification number: G09G3/20 ,  G09G2330/04 ,  G09G2330/06

Abstract: A display driving module including a driving circuit portion and a non-driving circuit portion is provided. The driving circuit portion is controlled by a system circuit block. The driving circuit portion includes driving channels for driving a display panel. First ESD protection devices are disposed in the driving circuit portion corresponding to the driving channels for providing at least one discharge path. The non-driving circuit portion electrically connects the system circuit block, the driving circuit portion and the display panel. At least one of second ESD protection devices is disposed in at least one of the driving circuit portion, the non-driving circuit portion, the system circuit block and the display panel corresponding to the first ESD protection devices. The second ESD protection devices cooperate with the first ESD protection devices to provide the discharge path. An image display system including the foregoing display driving module is also provided.

Abstract translation: 提供了包括驱动电路部分和非驱动电路部分的显示驱动模块。 驱动电路部分由系统电路块控制。 驱动电路部分包括用于驱动显示面板的驱动通道。 第一ESD保护装置设置在对应于驱动通道的驱动电路部分中，用于提供至少一个放电路径。 非驱动电路部分电连接系统电路块，驱动电路部分和显示面板。 至少一个第二ESD保护器件设置在驱动电路部分，非驱动电路部分，系统电路块和对应于第一ESD保护器件的显示面板中的至少一个中。 第二ESD保护装置与第一ESD保护装置配合以提供放电路径。 还提供了包括上述显示驱动模块的图像显示系统。

公开(公告)号：US20150280664A1

公开(公告)日：2015-10-01

申请号：US14741469

申请日：2015-06-17

Applicant: Novatek Microelectronics Corp.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Ju-Lin Huang

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2200/234 ,  H03F2203/45116

Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

Abstract translation: 提供了构造成驱动负载的运算放大器电路。 运算放大器电路包括输出级模块。 输出级模块包括检测电路和输出级电路。 检测电路被配置为基于当前输入电压和电流输出电压的比较结果来检测电流输出电压和先前的输出电压。 检测电路基于检测结果增强负载的输出级电路的充电容量或放电容量。 此外，还提供了一种用于增强运算放大器电路的驱动能力的方法。

公开(公告)号：US20140139364A1

公开(公告)日：2014-05-22

申请号：US13925849

申请日：2013-06-25

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: H03M1/66

CPC classification number: H03M1/06 ,  G09G3/20 ,  G09G2300/0421 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2320/0276 ,  H03M1/66 ,  H03M1/765

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract translation: 驱动电路包括多个参考电压线和数模转换器。 参考电压线被配置为分别传输不同的灰度参考电压，其中灰度参考电压被划分为至少两组，并且第一个参考电压的参考电压线中的至少一个参考电压线的线径/线宽 所述至少两组中的电压组与所述至少两组中的第二电压组的参考电压线的线径/线宽不同。 数模转换器耦合到参考电压线以接收灰度参考电压，并且用于根据灰度参考电压将数字信号转换成灰度级电压。

公开(公告)号：US10770011B2

公开(公告)日：2020-09-08

申请号：US15969763

申请日：2018-05-02

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Jhih-Siou Cheng

IPC: G09G3/36

Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a first polarity buffer, a negative polarity buffer. The first polarity buffer receives a first supply voltage and a second supply voltage to output a first reference voltage to a first resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.

公开(公告)号：US09569989B2

公开(公告)日：2017-02-14

申请号：US13928376

申请日：2013-06-26

Applicant: Novatek Microelectronics Corp.

Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

IPC: G09G3/00

CPC classification number: G09G3/00 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/0213 ,  G09G2310/0289 ,  G09G2330/045

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

Abstract translation: 提供面板驱动器集成电路（IC）和面板驱动器IC的冷却方法。 面板驱动器IC包括数据编码器，电平转换器，数模转换器（DAC），重排电路和输出缓冲器。 数据编码器接收并选择性地改变用于输出到电平移位器的原始数据。 电平移位器的输入端子和输出端子分别耦合到数据编码器的输出端子和DAC的数据输入端子。 重排电路的输出端分别耦合到DAC的参考电压输入端，以提供不同的参考电压。 重排电路根据数据编码器的操作相应地重新排列参考电压的顺序。 输出缓冲器的输入端耦合到DAC的输出端。