公开(公告)号：US20240168632A1

公开(公告)日：2024-05-23

申请号：US18081534

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: Apparatuses, systems, and techniques to facilitate asynchronous data movement accounting. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more memory transactions to be performed without storing information about the one or more memory transactions.

公开(公告)号：US20240161223A1

公开(公告)日：2024-05-16

申请号：US18086464

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Vishalkumar Ketankumar Mehta ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Chao Li ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06T1/20 ,  G06F9/54 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/541 ,  G06T1/60 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.

公开(公告)号：US12248788B2

公开(公告)日：2025-03-11

申请号：US17691690

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Prakash Bangalore Prabhakar ,  Gentaro Hirota ,  Ronny Krashinsky ,  Ze Long ,  Brian Pharris ,  Rajballav Dash ,  Jeff Tuckey ,  Jerome F. Duluk, Jr. ,  Lacky Shah ,  Luke Durant ,  Jack Choquette ,  Eric Werness ,  Naman Govil ,  Manan Patel ,  Shayani Deb ,  Sandeep Navada ,  John Edmondson ,  Greg Palmer ,  Wish Gandhi ,  Ravi Manyam ,  Apoorv Parle ,  Olivier Giroux ,  Shirish Gadre ,  Steve Heinrich

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54 ,  G06F13/16 ,  G06T1/60

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

公开(公告)号：US20240169472A1

公开(公告)日：2024-05-23

申请号：US18086484

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06T1/60 ,  G06F12/0811 ,  G06F12/0862 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0811 ,  G06F12/0862 ,  G06T1/20 ,  G06F2212/62

Abstract: Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more GPU caches.

公开(公告)号：US20240169467A1

公开(公告)日：2024-05-23

申请号：US18081559

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: Apparatuses, systems, and techniques to create one or more memory transaction software objects. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more software objects to indicate whether one or more memory transactions have been performed.

公开(公告)号：US20240168831A1

公开(公告)日：2024-05-23

申请号：US18086473

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Chao Li ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06F9/54

CPC classification number: G06F9/544

Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.

公开(公告)号：US20240168829A1

公开(公告)日：2024-05-23

申请号：US18086451

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Vishalkumar Ketankumar Mehta ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06F9/54

CPC classification number: G06F9/544

Abstract: Apparatuses, systems, and techniques to generate a tensor mapping. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a mapping from a first tensor to a second tensor to be generated.

公开(公告)号：US20240161224A1

公开(公告)日：2024-05-16

申请号：US18086469

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Vishalkumar Ketankumar Mehta ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Chao Li ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06T1/20 ,  G06F9/54 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/541 ,  G06T1/60

Abstract: Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about a memory transaction corresponding to the translation. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map without storing information about one or more memory transactions corresponding to the translation.

公开(公告)号：US20240161222A1

公开(公告)日：2024-05-16

申请号：US18086457

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Vishalkumar Ketankumar Mehta ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06T1/20 ,  G06F9/54 ,  G06F17/16 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/541 ,  G06F17/16 ,  G06T1/60

Abstract: Apparatuses, systems, and techniques to indicate how to generate image-to-column transformations. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate how to generate one or more image-to-column transformations.

公开(公告)号：US12204897B2

公开(公告)日：2025-01-21

申请号：US18072081

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.