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    Techniques for comprehensively synchronizing execution threads
    11.
    发明授权
    Techniques for comprehensively synchronizing execution threads 有权

    公开(公告)号：US10977037B2

    公开(公告)日：2021-04-13

    申请号：US16595398

    申请日：2019-10-07

    Applicant: NVIDIA Corporation

    Inventor： Ajay Sudarshan Tirumala ,  Olivier Giroux ,  Peter Nelson ,  Jack Choquette

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

    Abstract: In one embodiment, a synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.

    Thread-level sleep in a multithreaded architecture
    14.
    发明授权
    Thread-level sleep in a multithreaded architecture 有权

    公开(公告)号：US10817295B2

    公开(公告)日：2020-10-27

    申请号：US15582549

    申请日：2017-04-28

    Applicant: NVIDIA CORPORATION

    Inventor： Olivier Giroux ,  Peter Nelson ,  Jack Choquette ,  Ajay Sudarshan Tirumala

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

    Abstract: A streaming multiprocessor (SM) includes a nanosleep (NS) unit configured to cause individual threads executing on the SM to sleep for a programmer-specified interval of time. For a given thread, the NS unit parses a NANOSLEEP instruction and extracts a sleep time. The NS unit then maps the sleep time to a single bit of a timer and causes the thread to sleep. When the timer bit changes, the sleep time expires, and the NS unit awakens the thread. The thread may then continue executing. The SM also includes a nanotrap (NT) unit configured to issue traps using a similar timing mechanism to that described above. For a given thread, the NT unit parses a NANOTRAP instruction and extracts a trap time. The NT unit then maps the trap time to a single bit of a timer. When the timer bit changes, the NT unit issues a trap.

    Techniques for comprehensively synchronizing execution threads
    15.
    发明授权
    Techniques for comprehensively synchronizing execution threads 有权

    公开(公告)号：US10437593B2

    公开(公告)日：2019-10-08

    申请号：US15499843

    申请日：2017-04-27

    Applicant: NVIDIA Corporation

    Inventor： Ajay Sudarshan Tirumala ,  Olivier Giroux ,  Peter Nelson ,  Jack Choquette

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

    Abstract: A synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.

    Techniques for efficiently performing data reductions in parallel processing units
    19.
    发明授权
    Techniques for efficiently performing data reductions in parallel processing units 有权

    公开(公告)号：US11061741B2

    公开(公告)日：2021-07-13

    申请号：US16513393

    申请日：2019-07-16

    Applicant: NVIDIA CORPORATION

    Inventor： Peter Nelson ,  Olivier Giroux ,  Ajay Sudarshan Tirumala

    IPC: G06F9/46 ,  G06F9/52

    Abstract: Techniques are disclosed for reducing the latency associated with performing data reductions in a multithreaded processor. In response to a single instruction associated with a set of threads executing in the multithreaded processor, a warp reduction unit acquires register values stored in source registers, where each register value is associated with a different thread included in the set of threads. The warp reduction unit performs operation(s) on the register values to compute an aggregate value. The warp reduction unit stores the aggregate value in a destination register that is accessible to at least one of the threads in the set of threads. Because the data reduction is performed via a single instruction using hardware specialized for data reductions, the number of cycles required to perform the data reduction is decreased relative to prior-art techniques that are performed via multiple instructions using hardware that is not specialized for data reductions.

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