公开(公告)号：US20240013471A1

公开(公告)日：2024-01-11

申请号：US18471651

申请日：2023-09-21

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T17/005

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20230368337A1

公开(公告)日：2023-11-16

申请号：US18182271

申请日：2023-03-10

Applicant: NVIDIA CORPORATION

Inventor： Tero Tapani KARRAS ,  Miika AITTALA ,  Timo Oskari AILA ,  Samuli LAINE

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: Techniques are disclosed herein for generating a content item. The techniques include receiving a content item and metadata indicating a level of corruption associated with the content item; and for each iteration included in a plurality of iterations: performing one or more operations to add corruption to a first version of the content item to generate a second version of the content item, and performing one or more operations to reduce corruption in the second version of the content item to generate a third version of the content item, wherein a level of corruption associated with the third version of the content item is less than a level of corruption associated with the first version of the content item.

公开(公告)号：US20250104332A1

公开(公告)日：2025-03-27

申请号：US18971672

申请日：2024-12-06

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20250004947A1

公开(公告)日：2025-01-02

申请号：US18882707

申请日：2024-09-11

Applicant: NVIDIA Corporation

Inventor： Gregory A. MUTHLER ,  Timo AILA ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06F12/0875 ,  G06F16/901 ,  G06T15/06

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.

公开(公告)号：US20230368073A1

公开(公告)日：2023-11-16

申请号：US18182283

申请日：2023-03-10

Applicant: NVIDIA CORPORATION

Inventor： Tero Tapani KARRAS ,  Miika AITTALA ,  Timo Oskari AILA ,  Samuli LAINE

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: Techniques are disclosed herein for generating a content item. The techniques include receiving a content item and metadata indicating a level of corruption associated with the content item; and for each iteration included in a plurality of iterations: performing one or more operations to add corruption to a first version of the content item to generate a second version of the content item, and performing one or more operations to reduce corruption in the second version of the content item to generate a third version of the content item, wherein a level of corruption associated with the third version of the content item is less than a level of corruption associated with the first version of the content item.

公开(公告)号：US20240161250A1

公开(公告)日：2024-05-16

申请号：US18485239

申请日：2023-10-11

Applicant: NVIDIA CORPORATION

Inventor： Yogesh BALAJI ,  Timo Oskari AILA ,  Miika AITTALA ,  Bryan CATANZARO ,  Xun HUANG ,  Tero Tapani KARRAS ,  Karsten KREIS ,  Samuli LAINE ,  Ming-Yu LIU ,  Seungjun NAH ,  Jiaming SONG ,  Arash VAHDAT ,  Qinsheng ZHANG

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: Techniques are disclosed herein for generating a content item. The techniques include performing one or more first denoising operations based on an input and a first machine learning model to generate a first content item, and performing one or more second denoising operations based on the input, the first content item, and a second machine learning model to generate a second content item, where the first machine learning model is trained to denoise content items having an amount of corruption within a first corruption range, the second machine learning model is trained to denoise content items having an amount of corruption within a second corruption range, and the second corruption range is lower than the first corruption range.

公开(公告)号：US20230410410A1

公开(公告)日：2023-12-21

申请号：US18239876

申请日：2023-08-30

Applicant: NVIDIA Corporation

Inventor： Samuli LAINE ,  Tero KARRAS ,  Greg MUTHLER ,  William Parsons Newhall, JR. ,  Ronald Charles BABACH, JR. ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/21

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to provide a deterministic result of intersected triangles regardless of the order that the memory subsystem returns triangle range blocks for processing, while opportunistically eliminating alpha intersections that lie further along the length of the ray than closer opaque intersections.

公开(公告)号：US20200160588A1

公开(公告)日：2020-05-21

申请号：US16749089

申请日：2020-01-22

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06T15/06

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.

公开(公告)号：US20200050550A1

公开(公告)日：2020-02-13

申请号：US16101109

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Timo AILA ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL ,  Ronald Charles BABICH ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06F12/0875 ,  G06T15/06 ,  G06F17/30

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.

公开(公告)号：US20240355039A1

公开(公告)日：2024-10-24

申请号：US18761820

申请日：2024-07-02

Applicant: NVIDIA Corporation

Inventor： Samuli LAINE ,  Tero KARRAS ,  Timo AILA ,  Robert OHANNESSIAN ,  William Parsons NEWHALL, Jr. ,  Greg MUTHLER ,  Ian KWONG ,  Peter NELSON ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to properly handle numerically challenging computations at or near edges and/or vertices of primitives and/or ensure that a single intersection is reported when a ray intersects a surface formed by primitives at or near edges and/or vertices of the primitives.