公开(公告)号：US20160071770A1

公开(公告)日：2016-03-10

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/306 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

Abstract translation: 与示例性实施例一致，从具有有源器件和背面的正面的晶片衬底制备集成电路（IC）器件管芯的方法包括将晶片的前侧安装到保护箔上。 在第一聚焦深度处将激光施加到晶片背面上的锯道区域以限定修改区域; 修改区域在活动设备边界内的预定深度和由锯道区域限定的活动设备边界中定义。 保护箔被拉伸以将IC器件管芯彼此分开并暴露有源器件侧壁。 通过对有源器件侧壁的干蚀刻，基本上去除了改质区。

公开(公告)号：US08895363B2

公开(公告)日：2014-11-25

申请号：US13833906

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Michael Zernack

IPC: H01L21/44 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.

Abstract translation: 与示例性实施例一致，存在从晶片衬底组装晶片级芯片级处理（WLCSP）器件的方法，该方法包括将晶片衬底的背面磨削至规定厚度。 多个沟槽沿着晶片的背面表面上的多个器件裸片边界锯切，沟槽具有斜面形状。 多个沟槽被蚀刻直到多个沟槽的斜面轮廓为圆形。

公开(公告)号：US20230061529A1

公开(公告)日：2023-03-02

申请号：US18047329

申请日：2022-10-18

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: H01L21/683 ,  H01L21/673

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US11508606B2

公开(公告)日：2022-11-22

申请号：US16674399

申请日：2019-11-05

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: B29C65/00 ,  H01L21/683 ,  H01L21/673 ,  B29C65/56 ,  B29C65/58 ,  B29C65/50

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US20210134647A1

公开(公告)日：2021-05-06

申请号：US16674399

申请日：2019-11-05

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: H01L21/683 ,  H01L21/673

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US09601437B2

公开(公告)日：2017-03-21

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

公开(公告)号：US08809166B2

公开(公告)日：2014-08-19

申请号：US13721674

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Martin Lapke ,  Guido Albermann ,  Thomas Rohleder

IPC: H01L21/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50

Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.

Abstract translation: 描述了用于处理半导体晶片的方法和系统的实施例。 在一个实施例中，用于处理半导体晶片的方法包括在半导体晶片上执行激光隐形切割以在半导体晶片内形成隐形切割层，并且在执行激光隐形切割之后，从半导体的背面清洗半导体晶片 具有刀片的晶片以去除隐形切割层的至少一部分。 还描述了其它实施例。