公开(公告)号：US11721586B2

公开(公告)日：2023-08-08

申请号：US16721083

申请日：2019-12-19

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Ernst Eiper ,  Johannes Cobussen ,  Chantal Dijkstra

IPC: H01L21/82 ,  G01R31/28 ,  H01L21/66

CPC classification number: H01L21/82 ,  G01R31/2831 ,  G01R31/2856 ,  H01L22/32 ,  H01L22/34

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

公开(公告)号：US20210134648A1

公开(公告)日：2021-05-06

申请号：US16843461

申请日：2020-04-08

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Johannes Cobussen

IPC: H01L21/683 ,  H01L21/677

Abstract: A technique for handling an integrated circuit tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit tape assembly on a film frame carrier (FFC) frame, stretching the dicing tape while on the FFC frame, and securing the stretched dicing tape by engaging a spring ring with the dicing tape and FFC frame. Adjacent integrated circuits are thereby inhibited from colliding during shipment or storage for subsequent processing.

公开(公告)号：US10896878B2

公开(公告)日：2021-01-19

申请号：US16444322

申请日：2019-06-18

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Johannes Cobussen ,  Christian Zenz ,  Guido Albermann

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/58 ,  H01L23/52 ,  H01L21/66 ,  H01L21/304

Abstract: A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.

公开(公告)号：US12142527B2

公开(公告)日：2024-11-12

申请号：US18334421

申请日：2023-06-14

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Ernst Eiper ,  Johannes Cobussen ,  Chantal Claude Dijkstra

IPC: H01L21/82 ,  G01R31/28 ,  H01L21/66

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

公开(公告)号：US11881425B2

公开(公告)日：2024-01-23

申请号：US18047329

申请日：2022-10-18

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: B29C65/00 ,  H01L21/683 ,  H01L21/673 ,  B29C65/56 ,  B29C65/58 ,  B29C65/50

CPC classification number: H01L21/6836 ,  H01L21/673 ,  B29C65/50 ,  B29C65/565 ,  B29C65/58 ,  H01L21/6838 ,  H01L2221/68327

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US20230326796A1

公开(公告)日：2023-10-12

申请号：US18334421

申请日：2023-06-14

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Ernst Eiper ,  Johannes Cobussen ,  Chantal Claude Dijkstra

IPC: H01L21/82 ,  G01R31/28 ,  H01L21/66

CPC classification number: H01L21/82 ,  G01R31/2856 ,  G01R31/2831 ,  H01L22/32 ,  H01L22/34

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

公开(公告)号：US20210193524A1

公开(公告)日：2021-06-24

申请号：US16721083

申请日：2019-12-19

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Ernst Eiper ,  Johannes Cobussen ,  Chantal Dijkstra

IPC: H01L21/82 ,  G01R31/28 ,  H01L21/66

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

公开(公告)号：US11658056B2

公开(公告)日：2023-05-23

申请号：US16843461

申请日：2020-04-08

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Johannes Cobussen

IPC: B29C65/00 ,  H01L21/683 ,  H01L21/677 ,  H01L23/00 ,  C09J7/20 ,  B29C65/50 ,  B29C65/52 ,  B29C65/58 ,  B29C65/56

CPC classification number: H01L21/6836 ,  C09J7/20 ,  H01L21/6779 ,  H01L21/67763 ,  H01L24/01 ,  B29C65/50 ,  B29C65/526 ,  B29C65/565 ,  B29C65/58 ,  H01L21/6838

Abstract: A technique for handling an integrated circuit tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit tape assembly on a film frame carrier (FFC) frame, stretching the dicing tape while on the FFC frame, and securing the stretched dicing tape by engaging a spring ring with the dicing tape and FFC frame. Adjacent integrated circuits are thereby inhibited from colliding during shipment or storage for subsequent processing.

公开(公告)号：US20230061529A1

公开(公告)日：2023-03-02

申请号：US18047329

申请日：2022-10-18

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: H01L21/683 ,  H01L21/673

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

公开(公告)号：US11508606B2

公开(公告)日：2022-11-22

申请号：US16674399

申请日：2019-11-05

Applicant: NXP B.V.

Inventor： Antonius Hendrikus Jozef Kamphuis ,  Guido Albermann ,  Johannes Cobussen

IPC: B29C65/00 ,  H01L21/683 ,  H01L21/673 ,  B29C65/56 ,  B29C65/58 ,  B29C65/50

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.