公开(公告)号：US20150104931A1

公开(公告)日：2015-04-16

申请号：US14055188

申请日：2013-10-16

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Heiko Backer

IPC: H01L21/78 ,  B28D5/00

CPC classification number: H01L21/78 ,  B28D1/221 ,  B28D5/0041 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  Y10T225/287 ,  Y10T225/298

Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.

Abstract translation: 公开了一种用于晶片切割的装置，装置和方法。 在一个示例中，该装置公开了：具有第一温度的晶片保持装置; 可移动地联接到晶片保持装置的模具分离杆; 以及联接到所述设备并具有第二温度的冷却装置，其使得能够使所述模具分离杆响应于相对于所述晶片保持装置的运动而破坏附着材料。 在另一示例中，该方法公开了：接收具有施加到晶片一侧的附着材料的晶片; 将晶片放置在具有第一温度的保持装置中; 推动模具分离杆朝向晶片; 并将附着材料冷却至低于第一温度的第二温度，直到附着材料响应于推动而断裂。

公开(公告)号：US09601437B2

公开(公告)日：2017-03-21

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

公开(公告)号：US08987057B2

公开(公告)日：2015-03-24

申请号：US14021708

申请日：2013-09-09

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth Van Gemert ,  Tonny Kamphuis ,  Hartmut Buenning ,  Christian Zenz

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/28 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/96 ,  H01L24/97 ,  H01L41/338 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Abstract translation: 与示例性实施例一致，存在组装以抵抗机械损坏的半导体器件。 半导体器件包括限定在顶表面上的有源电路，提供与有源电路的电连接的接触区域。 有一个基座结构，有源电路安装在基座结构的相对的底面上; 基座结构的面积小于有源器件的面积。 由模制化合物组成的封装围绕有源器件的侧面和下侧并且围绕接触区域。 封装提供了弹性表面，保护有源器件免受机械损坏。 该实施例的特征在于，接触区域可以具有限定在其上的焊料凸块。

公开(公告)号：US08809166B2

公开(公告)日：2014-08-19

申请号：US13721674

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Martin Lapke ,  Guido Albermann ,  Thomas Rohleder

IPC: H01L21/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50

Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.

Abstract translation: 描述了用于处理半导体晶片的方法和系统的实施例。 在一个实施例中，用于处理半导体晶片的方法包括在半导体晶片上执行激光隐形切割以在半导体晶片内形成隐形切割层，并且在执行激光隐形切割之后，从半导体的背面清洗半导体晶片 具有刀片的晶片以去除隐形切割层的至少一部分。 还描述了其它实施例。

公开(公告)号：US20180240707A1

公开(公告)日：2018-08-23

申请号：US15440522

申请日：2017-02-23

Applicant: NXP B.V.

Inventor： Hartmut Buenning

IPC: H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/29

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/293 ,  H01L23/3114 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side. The second trench extends to end of the first trench; The method further includes applying a protective layer on the active side including filling the second trench with the material of the protective coating on the active side thus making a wall through a combination of the first trench and the second trench, the wall fully filled with the material of the protective layer on the backside and the protective layer on the active side and singulating each of the plurality of devices by cutting through the wall substantially in middle across a thickness of the wafer.

公开(公告)号：US20170148697A1

公开(公告)日：2017-05-25

申请号：US15342285

申请日：2016-11-03

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leo van Gemert ,  Hans van Rijckevorsel ,  Sascha Moeller ,  Hartmut Buenning ,  Steffen Holland ,  Y Kuang Huang

IPC: H01L23/31 ,  H01L29/06 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/683 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/32051 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/528 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10156 ,  H01L2924/17747 ,  H01L2924/35 ,  H01L2924/37

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

公开(公告)号：US20170092540A1

公开(公告)日：2017-03-30

申请号：US14871482

申请日：2015-09-30

Applicant: NXP B.V.

Inventor： Thomas Rohleder ,  Hartmut Buenning ,  Guido Albermann ,  Sascha Moeller ,  Martin Lapke

IPC: H01L21/82 ,  H01L21/304 ,  H01L23/528 ,  H01L21/66 ,  H01L27/04 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/82 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/12 ,  H01L23/528 ,  H01L27/04

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

公开(公告)号：US10347534B2

公开(公告)日：2019-07-09

申请号：US15701849

申请日：2017-09-12

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Michael Zernack ,  Leo M. Higgins, III

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/683

Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.

公开(公告)号：US20190080963A1

公开(公告)日：2019-03-14

申请号：US15701849

申请日：2017-09-12

Applicant: NXP B.V.

Inventor： Martin LAPKE ,  Hartmut Buenning ,  Sascha MOELLER ,  Guido ALBERMANN ,  Michael ZERNACK ,  Leo M. HIGGINS, III

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

CPC classification number: H01L21/78 ,  B23K26/00 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6836 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.

公开(公告)号：US09812361B2

公开(公告)日：2017-11-07

申请号：US14204858

申请日：2014-03-11

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Martin Lapke ,  Thomas Rohleder

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/784 ,  H01L21/268

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.