公开(公告)号：US20170092540A1

公开(公告)日：2017-03-30

申请号：US14871482

申请日：2015-09-30

Applicant: NXP B.V.

Inventor： Thomas Rohleder ,  Hartmut Buenning ,  Guido Albermann ,  Sascha Moeller ,  Martin Lapke

IPC: H01L21/82 ,  H01L21/304 ,  H01L23/528 ,  H01L21/66 ,  H01L27/04 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/82 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/12 ,  H01L23/528 ,  H01L27/04

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

公开(公告)号：US09812361B2

公开(公告)日：2017-11-07

申请号：US14204858

申请日：2014-03-11

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Martin Lapke ,  Thomas Rohleder

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/784 ,  H01L21/268

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

公开(公告)号：US20160172243A1

公开(公告)日：2016-06-16

申请号：US14566761

申请日：2014-12-11

Applicant: NXP B.V.

Inventor： Sascha Moeller ,  Thomas Rohleder ,  Guido Albermann ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  B23K26/364 ,  B23K26/402 ,  B23K10/00 ,  B24C1/04 ,  H01L21/3065 ,  H01J37/31 ,  H01J37/305 ,  H01J37/302 ,  H01L21/263 ,  H01L21/268 ,  B23K26/06 ,  B23K26/14

CPC classification number: H01L21/78 ,  B23K10/006 ,  B23K26/0626 ,  B23K26/14 ,  B23K26/364 ,  B23K26/402 ,  B23K2103/56 ,  B24C1/045 ,  H01J37/3023 ,  H01J37/305 ,  H01J37/31 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/67092

Abstract: One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and a second device structure having a second location; a material removal controller, coupled to the structures map, and having a material removal beam power level output signal and a material removal beam on/off status output signal; wherein the material removal controller is configured to select a first material removal beam power level and a first material removal beam on/off status corresponding to the first location; and wherein the material removal controller is configured to select a second material removal beam power level and a second material removal beam on/off status corresponding to the second location. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for wafer material removal.

Abstract translation: 一个实例公开了一种用于晶片材料去除的系统，包括：晶片结构图，识别具有第一位置的第一器件结构和具有第二位置的第二器件结构; 材料去除控制器，耦合到结构图，并具有材料去除光束功率电平输出信号和材料去除光束开/关状态输出信号; 其中所述材料去除控制器被配置为选择对应于所述第一位置的第一材料去除束功率水平和第一材料去除束开/关状态; 并且其中所述材料去除控制器被配置为选择对应于所述第二位置的第二材料去除束功率水平和第二材料去除束开/关状态。 另一个实例公开了一种制品，其包括至少一个非暂时的，有形的机器可读存储介质，其包含用于晶片材料去除的可执行机器指令。

公开(公告)号：US20150104931A1

公开(公告)日：2015-04-16

申请号：US14055188

申请日：2013-10-16

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Heiko Backer

IPC: H01L21/78 ,  B28D5/00

CPC classification number: H01L21/78 ,  B28D1/221 ,  B28D5/0041 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  Y10T225/287 ,  Y10T225/298

Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.

Abstract translation: 公开了一种用于晶片切割的装置，装置和方法。 在一个示例中，该装置公开了：具有第一温度的晶片保持装置; 可移动地联接到晶片保持装置的模具分离杆; 以及联接到所述设备并具有第二温度的冷却装置，其使得能够使所述模具分离杆响应于相对于所述晶片保持装置的运动而破坏附着材料。 在另一示例中，该方法公开了：接收具有施加到晶片一侧的附着材料的晶片; 将晶片放置在具有第一温度的保持装置中; 推动模具分离杆朝向晶片; 并将附着材料冷却至低于第一温度的第二温度，直到附着材料响应于推动而断裂。

公开(公告)号：US09601437B2

公开(公告)日：2017-03-21

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/306 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

公开(公告)号：US08809166B2

公开(公告)日：2014-08-19

申请号：US13721674

申请日：2012-12-20

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Martin Lapke ,  Guido Albermann ,  Thomas Rohleder

IPC: H01L21/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50

Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.

Abstract translation: 描述了用于处理半导体晶片的方法和系统的实施例。 在一个实施例中，用于处理半导体晶片的方法包括在半导体晶片上执行激光隐形切割以在半导体晶片内形成隐形切割层，并且在执行激光隐形切割之后，从半导体的背面清洗半导体晶片 具有刀片的晶片以去除隐形切割层的至少一部分。 还描述了其它实施例。

公开(公告)号：US09847258B2

公开(公告)日：2017-12-19

申请号：US14871482

申请日：2015-09-30

Applicant: NXP B.V.

Inventor： Thomas Rohleder ,  Hartmut Buenning ,  Guido Albermann ,  Sascha Moeller ,  Martin Lapke

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/311 ,  H01L21/66 ,  H01L27/04 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/12 ,  H01L23/528 ,  H01L27/04

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

公开(公告)号：US09349645B2

公开(公告)日：2016-05-24

申请号：US14055188

申请日：2013-10-16

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Heiko Backer

IPC: H01L21/00 ,  H01L21/78 ,  B28D5/00 ,  B28D1/22 ,  H01L21/683 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/78 ,  B28D1/221 ,  B28D5/0041 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  Y10T225/287 ,  Y10T225/298

Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.

Abstract translation: 公开了一种用于晶片切割的装置，装置和方法。 在一个示例中，该装置公开了：具有第一温度的晶片保持装置; 可移动地联接到晶片保持装置的模具分离杆; 以及联接到所述设备并具有第二温度的冷却装置，其使得能够使所述模具分离杆响应于相对于所述晶片保持装置的运动而破坏附着材料。 在另一示例中，该方法公开了：接收具有施加到晶片一侧的附着材料的晶片; 将晶片放置在具有第一温度的保持装置中; 推动模具分离杆朝向晶片; 并将附着材料冷却至低于第一温度的第二温度，直到附着材料响应于推动而断裂。

公开(公告)号：US20160071770A1

公开(公告)日：2016-03-10

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/306 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

Abstract translation: 与示例性实施例一致，从具有有源器件和背面的正面的晶片衬底制备集成电路（IC）器件管芯的方法包括将晶片的前侧安装到保护箔上。 在第一聚焦深度处将激光施加到晶片背面上的锯道区域以限定修改区域; 修改区域在活动设备边界内的预定深度和由锯道区域限定的活动设备边界中定义。 保护箔被拉伸以将IC器件管芯彼此分开并暴露有源器件侧壁。 通过对有源器件侧壁的干蚀刻，基本上去除了改质区。

公开(公告)号：US08895363B2

公开(公告)日：2014-11-25

申请号：US13833906

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Michael Zernack

IPC: H01L21/44 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.

Abstract translation: 与示例性实施例一致，存在从晶片衬底组装晶片级芯片级处理（WLCSP）器件的方法，该方法包括将晶片衬底的背面磨削至规定厚度。 多个沟槽沿着晶片的背面表面上的多个器件裸片边界锯切，沟槽具有斜面形状。 多个沟槽被蚀刻直到多个沟槽的斜面轮廓为圆形。