公开(公告)号：US11545982B2

公开(公告)日：2023-01-03

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US20220278938A1

公开(公告)日：2022-09-01

申请号：US17504794

申请日：2021-10-19

Applicant: NXP B.V.

Inventor： Khurram Waheed ,  Yaoqiao Li

IPC: H04L12/807 ,  H04W56/00

Abstract: Disclosed is a method of operating a low power wireless receiver in which a radio is periodically operable for receive intervals with sleep intervals therebetween and comprising a sleep clock having a sleep clock accuracy. A first transmission or packet is received. Based on a start moment of the first received packet, and an expected interval between packets, a nominal start moment is determined to start the radio for a packet window until a nominal end moment, for receiving a second packet; the packet window duration is extended in dependence on an estimated drift based on the SCA to provide a widened window. A start moment of a second received packet is measured within the widened window. An actual drift is calculated, from the start moment of the second packet; and an actual start moment and an actual window duration is determined, for receiving a third packet, based on the actual drift.

公开(公告)号：US20250094645A1

公开(公告)日：2025-03-20

申请号：US18969394

申请日：2024-12-05

Applicant: NXP B.V.

Inventor： Khurram Waheed

IPC: G06F21/72 ,  G06F21/60 ,  G06F21/62

Abstract: Securing protocol keys in a communication node comprises transferring a protocol access key stored in a secure enclave of a secure host platform to a secure key store in a communication platform via a secure transfer. The protocol access key which is plaintext is secure from access by a host processor of the secure host platform. A protocol key stored in the secure enclave is encrypted to an encrypted protocol key. The encrypted protocol key is transferred from the secure enclave to the communication platform over an unsecure bus. The encrypted protocol key is deciphered based on the protocol access key in the communication platform to form the protocol key. The protocol key which is plaintext is secured from access by the host processor, the communication controller, or both.

公开(公告)号：US11711764B2

公开(公告)日：2023-07-25

申请号：US17184035

申请日：2021-02-24

Applicant: NXP B.V.

Inventor： Khurram Waheed ,  Steven Michael Bosze

IPC: H04W52/02

CPC classification number: H04W52/0229

Abstract: A wireless communication system including a radio, a processing circuit including a processor and wake on radio circuitry. The wake on radio circuitry uses programmed descriptors to autonomously schedule transitioning into and out of sleep mode to periodically awaken and turn on the radio and perform at least one radio frequency deterministic function while the processor remains in a low power state. The deterministic functions may include a receive function, a transmit function, or a combination of both. The descriptors may be programmed according to any one of different scheduling modes supported by different communication protocols including a timeslot mode and a constant-interval mode. The wake on radio circuitry includes a scheduler that coordinates with protocol circuitry of the radio for performing one or more deterministic functions. The scheduler may program a sleep controller for scheduling sleep modes between communication sessions for performing the deterministic functions.

公开(公告)号：US20220321132A1

公开(公告)日：2022-10-06

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US20220311446A1

公开(公告)日：2022-09-29

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.