公开(公告)号：US12231136B2

公开(公告)日：2025-02-18

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/189 ,  H03C3/09 ,  H03L7/085 ,  H03L7/099 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

公开(公告)号：US11545982B2

公开(公告)日：2023-01-03

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US20220321132A1

公开(公告)日：2022-10-06

申请号：US17656124

申请日：2022-03-23

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/085 ,  H03L7/099

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

公开(公告)号：US20220311446A1

公开(公告)日：2022-09-29

申请号：US17655399

申请日：2022-03-18

Applicant: NXP B.V.

Inventor： Mathieu Perin ,  Stefano Dal Toso ,  Khurram Waheed ,  Claudio Gustavo Rey

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/10

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.