公开(公告)号：US08004014B2

公开(公告)日：2011-08-23

申请号：US12542263

申请日：2009-08-17

申请人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

发明人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

IPC分类号： H01L23/52 ,  H01L27/04

CPC分类号： H01L27/04 ,  H01L27/0207 ,  H01L27/11807

摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

摘要翻译： 提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。 单元格A和单元格B沿着单元边界彼此相邻。 相对于单元边界，金属互连的连接区域到单元边界没有其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

公开(公告)号：US07800151B2

公开(公告)日：2010-09-21

申请号：US11712469

申请日：2007-03-01

申请人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

发明人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

IPC分类号： H03K19/00 ,  H01L29/94

CPC分类号： H01L27/11807 ,  H01L27/0203

摘要： In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

摘要翻译： 在本发明中，提供了去耦电容电路，第一输出端子和第二输出端子。 去耦电容电路包括由第一Tr和第二Tr组成的TDDB控制电路和第三Tr。 第一和第二Tr的电导率类型彼此不同。 第一Tr的源极连接到第一电源布线，第一Tr的漏极连接到第二Tr的栅极。 第二Tr的源极连接到第二电源布线，第二Tr的漏极连接到第一Tr的栅极。 第三和第一Trs具有相同的导电类型。 第三Tr的源极和漏极连接到第一电源布线，第三Tr的栅极连接到第二Tr的漏极。 第一输出端子连接到第一Tr的漏极，第二输出端子连接到第二Tr的漏极。

公开(公告)号：US20090109330A1

公开(公告)日：2009-04-30

申请号：US12289232

申请日：2008-10-23

申请人： Takahiko Nakano ,  Toshiharu Inui ,  Hidetoshi Nishimura

发明人： Takahiko Nakano ,  Toshiharu Inui ,  Hidetoshi Nishimura

IPC分类号： H04N5/225

CPC分类号： G02B7/08 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A case member has a predetermined surface and a sealable inside, where a first circular area for passing light is provided at the center portion of the predetermined surface, a double-sided light shielding sheet, which is provided with a second circular area for passing light at the center, is adhered to the predetermined surface such that the second circular area is positioned in a concentric circle manner to the first circular area, the second circular area having a diameter smaller than the diameter of the first circular area, a transparent dustproof film is adhered on the light shielding sheet.

摘要翻译： 壳体构件具有预定表面和可密封的内部，其中用于通过光的第一圆形区域设置在预定表面的中心部分处，双面遮光片设置有用于通过光的第二圆形区域 在中心处粘附到预定表面，使得第二圆形区域以与第一圆形区域同心圆的方式定位，第二圆形区域的直径小于第一圆形区域的直径，透明防尘膜 粘附在遮光片上。

公开(公告)号：US20080169487A1

公开(公告)日：2008-07-17

申请号：US11968894

申请日：2008-01-03

申请人： Hiroyuki Shimbo ,  Hidetoshi Nishimura

发明人： Hiroyuki Shimbo ,  Hidetoshi Nishimura

IPC分类号： H01L27/10

CPC分类号： H01L27/0207

摘要： In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent transistors, a CA via is provided on the common source diffusion region, and a source wiring connected to the CA via is provided on the common source diffusion region. An inter-drain wiring connecting the drain regions of the two transistors is formed in a wiring layer higher than the source wiring. Therefore, the wiring path of the source wiring is not limited by the wiring path of the inter-drain wiring, and can be provided, covering the common source diffusion region to a further extent. As a result, the number of high-resistance CA vias or the flexibility of arrangement is increased, leading to a reduction in source resistance, resulting in an increase in operating speed of the semiconductor integrated circuit.

摘要翻译： 在半导体集成电路的布局结构中，当晶体管以恒定栅极布线间距排列时，在两个相邻晶体管之间设置公共源极扩散区，在公共源极扩散区上设置有CA通孔，并且源极布线连接 到CA通孔设置在公共源极扩散区域上。 连接两个晶体管的漏极区域的漏极间布线形成在比源极布线高的布线层中。 因此，源极配线的布线路径不受限制于漏极间配线的布线路径，能够进一步覆盖公共源极扩散区域。 结果，高电阻CA通孔的数量或布置的灵活性增加，导致源极电阻的降低，导致半导体集成电路的工作速度的增加。

公开(公告)号：US08159013B2

公开(公告)日：2012-04-17

申请号：US12524998

申请日：2009-02-24

申请人： Hidetoshi Nishimura ,  Hiroyuki Shimbo ,  Tetsurou Toubou ,  Hiroki Taniguchi ,  Hisako Yoneda

发明人： Hidetoshi Nishimura ,  Hiroyuki Shimbo ,  Tetsurou Toubou ,  Hiroki Taniguchi ,  Hisako Yoneda

IPC分类号： H01L29/66 ,  H01L29/94 ,  H01L21/108

CPC分类号： H01L27/0207 ,  H01L23/522 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

摘要翻译： 提供了一种半导体集成电路的布局结构，其能够防止金属布线在细胞边界附近的细化和线断裂，而不涉及用于OPC校正和OPC处理时间的数据量的增加。 在放置在第一方向上延伸的电源线和接地线之间的区域中，分别具有用于实现电路功能的晶体管和单元间线路的第一和第二单元彼此相邻 在第一个方向。 在第一和第二单元之间的边界部分中，放置沿与第一方向正交的第二方向延伸的金属布线，以便不使电源线和接地线短路。

公开(公告)号：US07932610B2

公开(公告)日：2011-04-26

申请号：US12397883

申请日：2009-03-04

申请人： Hidetoshi Nishimura

发明人： Hidetoshi Nishimura

IPC分类号： H01L23/52

CPC分类号： H01L21/76838 ,  H01L27/11807

摘要： In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

摘要翻译： 在包括多个单电池的半导体集成电路中，在格状的上电源线和下电池电源线之间配置辅助电源线，用于从上电源 连接到下电池电源线。 辅助电源线和下电池电源线通过两个通孔连接。 辅助电源线和上电源线通过单个通孔连接。 辅助电源线的电流由两个通孔分开，然后提供给下电池电源线。 因此，当从上电源线向下电池电源线供电时，下电池电源线到通孔的连接点处的电流集中减少，从而减少由EM（ 电迁移）。

公开(公告)号：US20100001404A1

公开(公告)日：2010-01-07

申请号：US12542263

申请日：2009-08-17

申请人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

发明人： Tomoaki Ikegami ,  Hidetoshi Nishimura ,  Kazuyuki Nakanishi

IPC分类号： H01L23/52

CPC分类号： H01L27/04 ,  H01L27/0207 ,  H01L27/11807

摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

摘要翻译： 提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。 单元格A和单元格B沿着单元边界彼此相邻。 相对于单元边界，金属互连的连接区域与单元边界不存在其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

公开(公告)号：US20070205451A1

公开(公告)日：2007-09-06

申请号：US11712469

申请日：2007-03-01

申请人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

发明人： Emi Mizushino ,  Hidetoshi Nishimura ,  Junichi Yano

IPC分类号： H01L29/94

CPC分类号： H01L27/11807 ,  H01L27/0203

摘要： In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

摘要翻译： 在本发明中，提供了去耦电容电路，第一输出端子和第二输出端子。 去耦电容电路包括由第一Tr和第二Tr组成的TDDB控制电路和第三Tr。 第一和第二Tr的电导率类型彼此不同。 第一Tr的源极连接到第一电源布线，第一Tr的漏极连接到第二Tr的栅极。 第二Tr的源极连接到第二电源布线，第二Tr的漏极连接到第一Tr的栅极。 第三和第一Trs具有相同的导电类型。 第三Tr的源极和漏极连接到第一电源布线，第三Tr的栅极连接到第二Tr的漏极。 第一输出端子连接到第一Tr的漏极，第二输出端子连接到第二Tr的漏极。

公开(公告)号：US20070200238A1

公开(公告)日：2007-08-30

申请号：US11703626

申请日：2007-02-08

申请人： Tomoaki Ikegami ,  Hidetoshi Nishimura

发明人： Tomoaki Ikegami ,  Hidetoshi Nishimura

IPC分类号： H01L23/48

CPC分类号： H01L27/0207 ,  H01L27/118

摘要： In a semiconductor integrated circuit apparatus formed by a core cell constituting a circuit function and a power wiring cell including a power wiring, a metal of a power wiring unit cell constituting the power wiring cell is formed to take a shape of T, and the power wiring unit cell is disposed adjacently, thereby forming a serial power wiring. The core cell and the power wiring cell are connected to each other through a metal wiring in the core cell in which coordinates in a horizontal direction are preset, and a power signal is thus supplied.

摘要翻译： 在由构成电路功能的核心单元形成的半导体集成电路装置和包括电力布线的电力布线单元构成的构成电力布线单元的电力布线单元的金属形成为T的形状， 接线单元相邻地配置，由此形成串联电力配线。 核心单元和电力线路单元通过在水平方向的坐标预置的核心单元中的金属布线彼此连接，从而提供电力信号。

公开(公告)号：US20050129384A1

公开(公告)日：2005-06-16

申请号：US11003340

申请日：2004-12-06

申请人： Katsuitsu Nishida ,  Tohru Shigeta ,  Hidetoshi Nishimura ,  Yoshinori Tanida

发明人： Katsuitsu Nishida ,  Tohru Shigeta ,  Hidetoshi Nishimura ,  Yoshinori Tanida

IPC分类号： G02B7/02 ,  G02B6/00 ,  G02B7/04 ,  G03B17/02 ,  G03B17/14 ,  H01L27/14 ,  H04N5/225 ,  H04N5/232 ,  H04N5/335

CPC分类号： H04N5/2254

摘要： An optical structure is disposed on a surface of a device substrate, and a lens system for introducing external light into a solid-state image pickup device is placed in the center of the optical structure. The outer shape of the optical structure seen from the light incident side of the lens system is rectangular, and its plane shape forms a rectangular frame section. An intermediate structure is disposed between the device substrate and the optical structure. The intermediate structure has a fitting section for fitting the optical structure in a part of side faces of the frame section.

摘要翻译： 光学结构设置在器件基板的表面上，并且将外部光引入固态图像拾取器件的透镜系统放置在光学结构的中心。 从透镜系统的光入射侧观察的光学结构的外形为矩形，其平面形状形成矩形框架部。 中间结构设置在器件基板和光学结构之间。 中间结构具有用于将光学结构装配在框架部分的侧面的一部分中的装配部分。