公开(公告)号：US5608741A

公开(公告)日：1997-03-04

申请号：US156427

申请日：1993-11-23

Applicant: Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

Inventor： Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.

Abstract translation: 本发明公开了一种使用使用补码传输晶体管逻辑实现的4位XOR单元的快速奇偶校验位发生器。 对于22n个输入，其中n是任意正整数，奇偶校验位仅使用 4位XOR单元在n个阶段中生成。 对于22n + 1输入，其中n是任意的正整数，使用放置在最后一行中的n行和一个2位XOR单元中的 4位XOR单元产生奇偶校验位。 通过在XOR单元内使用NMOS晶体管逻辑来进一步增强XOR单元的工作速度。

公开(公告)号：US5581497A

公开(公告)日：1996-12-03

申请号：US325777

申请日：1994-10-17

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/506

CPC classification number: G06F7/506

Abstract: An adder is described. The adder generates a block generate signal after one domino gate delay. The adder can also generate a carry out signal, generate a first plurality of sum signals in response to the carry out signal, generate a block generate signal, generate a group generate signal, and generate a second plurality of sum signals in response to the carry out signal, block generate signal and group generate signal.

Abstract translation: 描述加法器。 加法器在一个多米诺门延迟后产生一个块生成信号。 加法器还可以生成进位信号，响应于进位信号产生第一多个和信号，产生块产生信号，产生组生成信号，并响应于进位产生第二多个和信号 输出信号，块生成信号和组生成信号。

公开(公告)号：US20220013154A1

公开(公告)日：2022-01-13

申请号：US17327602

申请日：2021-05-21

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G11C7/22 ,  G11C7/10 ,  G11C15/04

Abstract: An integrated circuit might comprise an input flip-flop block clocked by a first clock having a first clock period, an output of the input flip-flop block for outputting data clocked by the first clock, a first logic block implementing a desired logic function, an input of the first logic block, coupled to the input flip-flop block, an output flip-flop block clocked by a second clock having a period equal to the first clock period and derived from a common source as the first clock, and an input of the output flip-flop block, coupled to an output of the first logic block. A first logic block delay can be at least the first clock period plus a specified delay excess and the second clock can be delayed by at least the specified delay excess. The first logic block might be a portion of a CAM block and/or a TCAM block.

公开(公告)号：US06341099B1

公开(公告)日：2002-01-22

申请号：US09672950

申请日：2000-09-29

Applicant: Sudarshan Kumar ,  Sadhana Madhyastha ,  Gaurav G. Mehta ,  Jiann-Cherng James Lan

Inventor： Sudarshan Kumar ,  Sadhana Madhyastha ,  Gaurav G. Mehta ,  Jiann-Cherng James Lan

IPC: G11C700

CPC classification number: G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

Abstract: A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.

Abstract translation: 一种用于降低由多个数据单元组成的数据存储设备中的功耗的技术包括将数据单元的数量排列成簇，每个簇具有多个数据单元，其数据使能输入连接在一起。 提供数据写总线以向数据单元数量的数据使能输入提供数据使能信号。 在簇和写入数据总线之间分别设置多个通过门。 通过门有选择地使允许数据使能信号从写入数据总线传递到所选择的一个或多个集群的多个数据单元的数据使能输入。 多个反相器可以分别设置在通过门数和簇之间。 多个保持器电路可以分别连接到通孔的数量。 每个通过栅极可以包括一对场效应晶体管，其可以是互补场效应晶体管。 每个维持器电路可以包括一对背对背反相器。

公开(公告)号：US06266757B1

公开(公告)日：2001-07-24

申请号：US09074019

申请日：1998-05-06

Applicant: Mehul Desai ,  Sudarshan Kumar

Inventor： Mehul Desai ,  Sudarshan Kumar

IPC: G06F1206

CPC classification number: G06F7/509 ,  G06F7/607 ,  G06F9/355 ,  G06F9/3555

Abstract: A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number of exclusive-or logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.

Abstract translation: 公开了一种用于添加两个或多个数字并产生和和携带输出的电路。 加法器电路接收两个或多个要相加的数字。 加法器电路包括产生中间输出的多个异或逻辑电路。 中间输出输入到多米诺骨牌多路复用器。 多米诺骨牌多路复用器包括多路复用器门和并联连接的异或门。 多米诺骨牌多路复用器电路输出输入号码的和值和进位值。 时钟信号驱动复用器门和多米诺多路复用器电路中的异或门。 该时钟信号将要加到一起的数字的输入和多米诺多路复用器电路中的相加操作同步。

公开(公告)号：US6127850A

公开(公告)日：2000-10-03

申请号：US346108

申请日：1999-06-30

Applicant: Jiann-Cherng James Lan ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Sudarshan Kumar

IPC: H03K19/173 ,  H03K19/096

CPC classification number: H03K19/1731

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.

Abstract translation: 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享下拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 该电路可用于时钟缓冲应用。

公开(公告)号：US5471414A

公开(公告)日：1995-11-28

申请号：US32607

申请日：1993-03-17

Applicant: Sudarshan Kumar ,  Jashojiban Banik

Inventor： Sudarshan Kumar ,  Jashojiban Banik

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/38

CPC classification number: G06F7/506 ,  G06F7/507

Abstract: An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.

Abstract translation: 一个N位条件和加法器，由多个串联耦合的2位加法器组成。 2位加法器具有和产生电路，它从两个2位输入端计算两个和位。 每个和位由最多两个串联的多路复用器进行处理，用于对来自先前的2位加法器的任何进位进行分解，而不管要添加的N位的总数。 进位发生电路产生两个进位信号。 选择适当的进位信号以由由多个p-n通孔组成的多路复用器进行传播。 在输入到多路复用器之前，首先缓冲两个进位信号及其补码。 多路复用器输出适当的进位信号及其补码以输入到后续的2位加法器，并用于控制后续的多路复用器选择。

公开(公告)号：US4905180A

公开(公告)日：1990-02-27

申请号：US286227

申请日：1988-12-16

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/506

CPC classification number: G06F7/506 ,  G06F7/508

Abstract: A metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals for a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.

Abstract translation: 由多个四位片块制造的金属氧化物半导体（MOS）分区进位前瞻加法器。 每个块提供四个和信号并提供块进位信号。 块被组织成最佳尺寸的组，每组中具有逻辑以产生组传播信号。 每个块具有块载入线，其中单个晶体管连接在块的输入和输出端子之间。 块使用中间携带电路来计算总和代替全加器。 另外，存在一个主输送线，晶体管由32位加法器的组传播信号控制，进位链中的最大通过门延迟是三通道。

公开(公告)号：US11017858B1

公开(公告)日：2021-05-25

申请号：US15390500

申请日：2016-12-25

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G11C15/04

Abstract: A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.

公开(公告)号：US06952118B2

公开(公告)日：2005-10-04

申请号：US10324307

申请日：2002-12-18

Applicant: Shahram Jamshidi ,  Sudarshan Kumar

Inventor： Shahram Jamshidi ,  Sudarshan Kumar

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

Abstract translation: 在非活动状态下具有减小的漏电流的门时多米诺骨牌电路，其中多米诺骨牌电路中的多米诺级在预充电路径中具有长通道长度的晶体管。 在非活动状态期间，多米诺骨牌阶段被置于评估状态并被排除。