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16 条记录 (耗时 0.033 秒)

    Vertical Doping and Capacitive Balancing for Power Semiconductor Devices
    11.
    发明申请
    Vertical Doping and Capacitive Balancing for Power Semiconductor Devices 审中-公开
    功率半导体器件的垂直掺杂和电容平衡

    公开(公告)号：US20140273374A1

    公开(公告)日：2014-09-18

    申请号：US13842694

    申请日：2013-03-15

    申请人： Joseph Yedinak ,  Richard Stokes ,  Sukhendu Deb Roy ,  Steven Sapp

    发明人： Joseph Yedinak ,  Richard Stokes ,  Sukhendu Deb Roy ,  Steven Sapp

    IPC分类号： H01L29/66

    CPC分类号： H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7813

    摘要： Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.

    摘要翻译： 描述了功率半导体器件中的垂直掺杂和用于制造这种掺杂剂分布的方法。 所述方法包括提供半导体衬底，在衬底上提供外延层，所述外延层包含底部，该底部包含基本上恒定的第一浓度遍及整个底部的第一导电型掺杂剂; 和含有第二浓度低于第一浓度的第一导电型掺杂剂的上部; 在外延层中提供沟槽; 在沟槽中形成晶体管结构; 以及在与所述沟槽相邻的所述外延层的上部中形成阱区，所述阱区包含与所述第一导电类型相反的第二导电型掺杂剂。 描述其他实施例。

    Charge balance insulated gate bipolar transistor
    14.
    发明申请
    Charge balance insulated gate bipolar transistor 审中-公开
    电荷平衡绝缘栅双极晶体管

    公开(公告)号：US20070181927A1

    公开(公告)日：2007-08-09

    申请号：US11408812

    申请日：2006-04-21

    申请人： Joseph Yedinak ,  Kwang Oh ,  Chongman Yun ,  Jae Lee

    发明人： Joseph Yedinak ,  Kwang Oh ,  Chongman Yun ,  Jae Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7395 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7397

    摘要： An IGBT includes a first silicon region over a collector region, and a plurality of pillars of first and second conductivity types arranged in an alternating manner over the first silicon region. The IGBT further includes a plurality of well regions each extending over and being in electrical contact with one of the pillars of the first conductivity type, and a plurality of gate electrodes each extending over a portion of a corresponding well region. The physical dimensions of each of the first and second conductivity type pillars and the doping concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type.

    摘要翻译： IGBT包括在集电极区域上的第一硅区域和在第一硅区域上以交替方式布置的多个第一和第二导电类型的柱。 IGBT进一步包括多个阱区，每个阱区延伸并且与第一导电类型的一个柱中的一个电接触，并且多个栅电极各自延伸在对应的阱区的一部分上。 选择第一和第二导电型柱中的每一个的物理尺寸和第一和第二导电类型柱中的每一个中的载流子的掺杂浓度，以便在第一导电性的每个支柱中的净电荷和 其第二导电类型的相邻支柱中的净电荷。

    Method of isolating the current sense on power devices while maintaining a continuous stripe cell
    15.
    发明申请
    Method of isolating the current sense on power devices while maintaining a continuous stripe cell 有权
    在保持连续条形单元的同时隔离电源设备上的电流检测的方法

    公开(公告)号：US20050272209A1

    公开(公告)日：2005-12-08

    申请号：US11130794

    申请日：2005-05-17

    申请人： Joseph Yedinak ,  Dwayne Reichl ,  Douglas Lange

    发明人： Joseph Yedinak ,  Dwayne Reichl ,  Douglas Lange

    IPC分类号： H01L29/739 ,  H01L21/331

    CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/7395

    摘要： An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

    摘要翻译： 集成电路管芯包括具有源极掺杂剂和触点的有源区。 有源区金属层覆盖有源区。 感测区域设置在模具上。 感测区域金属层覆盖在感测区域上。 多个多晶硅栅极条，多晶硅开口和主体条被设置在管芯上，并以连续且不间断的方式从有源区延伸到感测区域中。 源掺杂剂和接触物被排除的第一区域围绕着感测区域的周边。 蚀刻区域设置在第一区域上，从而将感测区域金属层与有源区金属层分离并电隔离。