公开(公告)号：US20140273374A1

公开(公告)日：2014-09-18

申请号：US13842694

申请日：2013-03-15

申请人： Joseph Yedinak ,  Richard Stokes ,  Sukhendu Deb Roy ,  Steven Sapp

发明人： Joseph Yedinak ,  Richard Stokes ,  Sukhendu Deb Roy ,  Steven Sapp

IPC分类号： H01L29/66

CPC分类号： H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7813

摘要： Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.

摘要翻译： 描述了功率半导体器件中的垂直掺杂和用于制造这种掺杂剂分布的方法。 所述方法包括提供半导体衬底，在衬底上提供外延层，所述外延层包含底部，该底部包含基本上恒定的第一浓度遍及整个底部的第一导电型掺杂剂; 和含有第二浓度低于第一浓度的第一导电型掺杂剂的上部; 在外延层中提供沟槽; 在沟槽中形成晶体管结构; 以及在与所述沟槽相邻的所述外延层的上部中形成阱区，所述阱区包含与所述第一导电类型相反的第二导电型掺杂剂。 描述其他实施例。

公开(公告)号：US20050167742A1

公开(公告)日：2005-08-04

申请号：US11026276

申请日：2004-12-29

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： G06F1/26 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/68 ,  H01L23/495 ,  H01L23/498 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H02M3/00 ,  H02M3/335

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

摘要翻译： 公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。 本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。 本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。 根据本发明的其它方面提供了改进的功率器件制造方法。 提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。 根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。 本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

公开(公告)号：US20060214221A1

公开(公告)日：2006-09-28

申请号：US11445020

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：US20060214222A1

公开(公告)日：2006-09-28

申请号：US11445111

申请日：2006-05-31

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas Grebs ,  Nathan Kraft ,  Dean Probst ,  Rodney Ridley ,  Steven Sapp ,  Qi Wang ,  Chongman Yun ,  J. Lee ,  Peter Wilson ,  Joseph Yedinak ,  J. Jung ,  H. Jang ,  Babak Sani ,  Richard Stokes ,  Gary Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James Murphy ,  Gordon Madson ,  Bruce Marchant ,  Christopher Rexer ,  Christopher Kocon ,  Debra Woolsey

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

公开(公告)号：US20070082441A1

公开(公告)日：2007-04-12

申请号：US11551992

申请日：2006-10-23

申请人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

发明人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

摘要翻译： 场效应晶体管如下形成。 沟槽形成在第一导电类型的半导体区域中。 每个沟槽部分地填充有一种或多种材料。 执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。 进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。 然后在每个身体区域中形成第一导电类型的源区域。

公开(公告)号：US20060273386A1

公开(公告)日：2006-12-07

申请号：US11441386

申请日：2006-05-24

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

IPC分类号： H01L29/94

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 至少一个导电屏蔽电极设置在栅极沟槽中。 栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。 屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。 栅极电介质层使栅电极与体区绝缘。 屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

公开(公告)号：US20120248528A1

公开(公告)日：2012-10-04

申请号：US13492473

申请日：2012-06-08

申请人： Peter H. Wilson ,  Steven Sapp

发明人： Peter H. Wilson ,  Steven Sapp

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/7835

摘要： MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

摘要翻译： 用于RF应用的MOSFET器件，其使用沟槽栅极代替横向MOSFET器件中常规使用的横向栅极。 沟槽栅为高频增益提供单通道，短通道。 本发明的实施例提供了在沟槽栅极中具有不对称氧化物的器件，以及降低栅极 - 漏极电容以提高RF性能的LDD区域。 对这些TG-LDMOS器件的改进包括将源极屏蔽导体放置在栅极下方并将两个栅极放置在沟槽栅极区域中。 这些通过降低栅极 - 漏极电容来提高器件的高频性能。 进一步的改进包括向LDD区域添加电荷平衡区域并添加源到衬底或漏极到衬底的通孔。

公开(公告)号：US20110284955A1

公开(公告)日：2011-11-24

申请号：US13114253

申请日：2011-05-24

申请人： Steven Sapp ,  Peter H. Wilson

发明人： Steven Sapp ,  Peter H. Wilson

IPC分类号： H01L27/092

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

摘要： In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region.

摘要翻译： 根据本发明的实施例，MOSFET包括具有第一表面的第一半导体区域，从第一表面延伸到第一半导体区域的第一绝缘填充沟槽区域和沿着侧壁的半绝缘材料条带 的第一绝缘填充沟槽区域。 半绝缘材料的条可以与第一半导体区域绝缘​​。

公开(公告)号：US08044463B2

公开(公告)日：2011-10-25

申请号：US12755966

申请日：2010-04-07

申请人： Brian S. Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean E. Probst

发明人： Brian S. Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean E. Probst

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。

公开(公告)号：US20100264487A1

公开(公告)日：2010-10-21

申请号：US12755966

申请日：2010-04-07

申请人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

发明人： Brian Sze-Ki Mo ,  Duc Chau ,  Steven Sapp ,  Izak Bencuya ,  Dean Edward Probst

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

摘要翻译： 提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂 很好地围着沉重的身体下面的沉重的身体。