公开(公告)号：US09521348B2

公开(公告)日：2016-12-13

申请号：US14696120

申请日：2015-04-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Jie Shen ,  Min Qu ,  Hyunseok Lee

IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/378 ,  H04N5/374

Abstract: Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“ADCs”), a plurality of blocks of Static Random-Access Memory (“SRAM”), and a plurality of blocks of Dynamic Random-Access Memory (“DRAM”). The plurality ADCs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels. The plurality of blocks of SRAM is coupled to receive digital image signals from the ADCs. The digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels. The plurality of blocks of DRAM is coupled to the blocks of SRAM. Each block of SRAM is coupled to sequentially output the digital image signals to each of the blocks of DRAM. Each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals.

Abstract translation: 用于读出图像传感器像素阵列的读出电路包括：读出单元，其包括多个模数转换器（“ADC”），多个静态随机存取存储器块（“SRAM”），以及多个 动态随机存取存储器块（“DRAM”）。 多个ADC耦合到图像传感器像素阵列的读出模拟图像信号二维块。 多个SRAM块被耦合以从ADC接收数字图像信号。 数字图像信号表示从二维像素块读出的模拟图像信号。 DRAM的多个块耦合到SRAM块。 SRAM的每个块被耦合以顺序地将数字图像信号输出到DRAM的每个块。 每个读出单元被耦合以输出数字图像信号作为多个输入/输出（“IO”）信号。

公开(公告)号：US20150288908A1

公开(公告)日：2015-10-08

申请号：US14246859

申请日：2014-04-07

Applicant: OmniVision Technologies, Inc.

Inventor： Jie Shen

IPC: H04N5/3745 ,  G06F17/50 ,  H04N5/378

CPC classification number: G06F17/5072 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464

Abstract: A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.

Abstract translation: 公开了一种平面图优化的堆叠图像传感器和用于设计传感器的方法。 传感器层包括分成PSA组的多个PSA。 电路层包括多个模数转换器，每个转换器通信地耦合到不同的PSA。 每个模数转换器（ADC）与与其通信耦合的PSA相关联的PSA组半对齐。 ADC的平面布置图最大限度地提高了ADC不间断的电路层上的连续的基于全球的空间。 所得到的电路层平面图具有与包含ADC的一个或多个基于本地的空间交错的一个或多个基于全局的空间。

公开(公告)号：US20160366356A1

公开(公告)日：2016-12-15

申请号：US14738744

申请日：2015-06-12

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Jie Shen ,  Jizhang Shan

IPC: H04N5/378 ,  H04N5/355 ,  H04N5/235 ,  H04N5/353

CPC classification number: H04N5/378 ,  H04N5/2357 ,  H04N5/3532 ,  H04N5/35581

Abstract: A method of detecting light-emitting diode (LED) light starts with a control circuitry generating a shutter signal that is transmitted to a pixel array to control image acquisition by the pixel array and to establish a set exposure time. The readout circuitry may then read out the image data from the pixel array that includes reading out the image data from a plurality of successive and overlapped frames having the set exposure time. The set exposure time may be the same for each of the frames. The successive and overlapped frames may be interlaced frames. Other embodiments are also described.

Abstract translation: 检测发光二极管（LED）光的方法从产生快门信号的控制电路开始，该快门信号被传输到像素阵列以控制像素阵列的图像采集并建立设定的曝光时间。 读出电路然后可以从包括从具有设定的曝光时间的多个连续和重叠的帧中读出图像数据的像素阵列读出图像数据。 每个帧的设定曝光时间可以相同。 连续和重叠的帧可以是隔行帧。 还描述了其它实施例。

公开(公告)号：US20160330392A1

公开(公告)日：2016-11-10

申请号：US14707572

申请日：2015-05-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik ,  Howard E. Rhodes ,  Jie Shen

IPC: H04N5/378 ,  H04N5/369 ,  H04N5/3745

CPC classification number: H04N5/37457

Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Abstract translation: 图像传感器包括设置在第一半导体管芯中的像素阵列。 像素阵列被划分为多个像素子阵列。 多个像素子阵列中的每一个被排列成多个像素组。 多个像素组中的每一个被排列成像素单元的p×q阵列。 多个读出电路设置在第二半导体管芯中。 互连层堆叠在第一半导体管芯和第二半导体管芯之间。 互连层包括多个导体。 多个像素子阵列中的每一个通过多个导体中的相应一个耦合到多个读出电路中的对应的一个。