公开(公告)号：US20160330392A1

公开(公告)日：2016-11-10

申请号：US14707572

申请日：2015-05-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik ,  Howard E. Rhodes ,  Jie Shen

IPC: H04N5/378 ,  H04N5/369 ,  H04N5/3745

CPC classification number: H04N5/37457

Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Abstract translation: 图像传感器包括设置在第一半导体管芯中的像素阵列。 像素阵列被划分为多个像素子阵列。 多个像素子阵列中的每一个被排列成多个像素组。 多个像素组中的每一个被排列成像素单元的p×q阵列。 多个读出电路设置在第二半导体管芯中。 互连层堆叠在第一半导体管芯和第二半导体管芯之间。 互连层包括多个导体。 多个像素子阵列中的每一个通过多个导体中的相应一个耦合到多个读出电路中的对应的一个。

公开(公告)号：US09438866B2

公开(公告)日：2016-09-06

申请号：US14259567

申请日：2014-04-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik ,  Per Olaf Pahr

IPC: H04N5/235 ,  H04N5/335 ,  H04N9/083 ,  H04N9/04 ,  H04N5/343 ,  H04N5/345 ,  H04N5/347 ,  H04N5/3745

CPC classification number: H04N9/045 ,  H04N5/343 ,  H04N5/3458 ,  H04N5/347 ,  H04N5/37457 ,  H04N9/04511 ,  H04N2209/045

Abstract: Embodiments of an apparatus including a pixel array including a plurality of individual pixels grouped into pixel kernels having two or more individual pixels, wherein each pixel kernel includes a floating diffusion electrically coupled to all individual pixels in the kernel. A color filter array (CFA) is positioned over and optically coupled to the pixel array, the CFA comprising a plurality of tiled minimal repeating units, each including a plurality of scaled filters having a photoresponse selected from among two or more different photoresponses. Individual pixels within each pixel kernel are optically coupled to a scaled filter. Circuitry and logic coupled to the pixel array cause the apparatus to operate in a first mode wherein signals from a subset of individual pixels are individually transferred to their floating diffusion and read, resulting in a high-resolution, low-sensitivity sub-image and a second mode wherein signals from individual pixels in every pixel kernel are binned into the kernel's floating diffusion and read, resulting in a low-resolution, high-sensitivity image.

Abstract translation: 包括像素阵列的装置的实施例，其包括分组为具有两个或多个单独像素的像素核的多个单独像素，其中每个像素核包括电耦合到所述内核中的所有单独像素的浮动扩散。 滤色器阵列（CFA）位于像素阵列的上方并光学耦合，该CFA包括多个平铺的最小重复单元，每个最小重复单元包括具有选自两个或更多个不同光响应中的光响应的多个缩放滤镜。 每个像素内核中的各个像素光学耦合到缩放滤镜。 耦合到像素阵列的电路和逻辑使得装置以第一模式操作，其中来自各个像素的子集的信号被单独地转移到它们的浮动扩散和读取，导致高分辨率，低灵敏度的子图像和 第二模式，其中来自每个像素核心中的各个像素的信号被分样成内核的浮动扩散和读取，导致低分辨率，高灵敏度的图像。

公开(公告)号：US20140337669A1

公开(公告)日：2014-11-13

申请号：US13892019

申请日：2013-05-10

Applicant: Omnivision Technologies, Inc

Inventor： Johannes Solhusvik ,  Kristoffer Ellersgaard Koch ,  Sohrab Yaghmai ,  Jenny Picalausa

IPC: G06F11/263

CPC classification number: G11C29/08 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/2602

Abstract: A method for testing an electronic memory while the memory is in use includes: (a) detecting an access to the electronic memory at a test address, (b) saving, in a register subsystem, write data written to the electronic memory at a location corresponding to the test address, (c) comparing the write data to data read from the electronic memory at the location corresponding to the test address to determine whether the memory has a fault, and (d) generating an error signal if the memory has a fault.

Abstract translation: 一种用于在存储器使用期间测试电子存储器的方法包括：（a）在测试地址处检测对电子存储器的访问，（b）在寄存器子系统中保存在位置处写入电子存储器的写入数据 对应于测试地址，（c）将写入数据与在与测试地址相对应的位置处从电子存储器读取的数据进行比较，以确定存储器是否具有故障，以及（d）如果存储器具有 故障。

公开(公告)号：US20170041562A1

公开(公告)日：2017-02-09

申请号：US14821651

申请日：2015-08-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik

IPC: H04N5/378

CPC classification number: H04N5/378 ,  H04N5/35554 ,  H04N5/35581 ,  H04N5/37457

Abstract: Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.

Abstract translation: 在图像传感器中实现堆叠式芯片HDR算法的方法以具有第一曝光时间的第一帧的像素阵列捕获开始，并且具有比第一曝光时间长或短的第二曝光时间的第二帧。 像素阵列设置在第一半导体管芯中并被划分为像素子阵列。 每个像素子阵列被布置成像素组，并且每个像素组被布置成像素单元阵列。 设置在第二半导体管芯中的读出电路获取第一和第二帧的图像数据。 每个像素子阵列通过多个导体中的对应的一个连接到对应的读出电路。 ADC电路将图像数据从第一帧和第二帧转换为第一和第二ADC输出。 第二个半导体管芯上的功能逻辑增加了第一和第二个ADC输出，以产生最终的ADC输出。 还描述了其它实施例。

公开(公告)号：US09936153B1

公开(公告)日：2018-04-03

申请号：US15285352

申请日：2016-10-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Duli Mao ,  Trygve Willassen ,  Johannes Solhusvik ,  Keiji Mabuchi ,  Gang Chen ,  Sohei Manabe ,  Dyson H. Tai ,  Bill Phan ,  Oray Orkun Cellek ,  Zhiqiang Lin

IPC: H04N5/361 ,  H04N5/374 ,  H04N5/378 ,  H01L27/146

CPC classification number: H04N5/361 ,  H01L27/14636 ,  H01L27/14656 ,  H04N5/374 ,  H04N5/378

Abstract: Apparatuses and methods for image sensors with pixels that reduce or eliminate flicker induced by high intensity illumination are disclosed. An example image sensor may include a photodiode, a transfer gate, an anti-blooming gate, and first and second source follower transistors. The photodiode may capture light and generate charge in response, and the photodiode may have a charge capacity. The transfer gate may selectively transfer charge to a first floating diffusion, and the anti-blooming gate may selectively transfer excess charge to a second floating diffusion when the generated charge is greater than the photodiode charge capacity. The first source-follower transistor may be directly coupled to the first floating diffusion by a gate, the first source-follower to selectively output a first signal to a first bitline in response to enablement of a first row selection transistor, and the second source-follower transistor may be capacitively-coupled to the second floating diffusion, the second source-follower to selectively output a second signal to a second bitline in response to enablement of a second row selection transistor.

公开(公告)号：US09819889B2

公开(公告)日：2017-11-14

申请号：US14821651

申请日：2015-08-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik

IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/355

CPC classification number: H04N5/378 ,  H04N5/35554 ,  H04N5/35581 ,  H04N5/37457

Abstract: Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.

公开(公告)号：US20160093664A1

公开(公告)日：2016-03-31

申请号：US14500193

申请日：2014-09-29

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik ,  Dominic Massetti

IPC: H01L27/148

CPC classification number: H01L27/14831 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14643 ,  H04N5/2351 ,  H04N5/353 ,  H04N5/3535 ,  H04N5/3745 ,  H04N5/37452

Abstract: A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.

Abstract translation: 像素单元包括响应于入射光耦合到光生成图像电荷的光电二极管。 深沟槽隔离结构靠近光电二极管设置，以通过深沟槽隔离结构提供与光电二极管的电容耦合。 放大器晶体管耦合到深沟槽隔离结构以响应于通过由深沟槽隔离结构提供的电容耦合从光电二极管读出的图像电荷来产生放大的图像数据。 行选择晶体管耦合到放大器晶体管的输出，以选择性地将放大的图像数据输出到耦合到行选择晶体管的列位线。

公开(公告)号：US09202591B2

公开(公告)日：2015-12-01

申请号：US13892019

申请日：2013-05-10

Applicant: OmniVision Technologies, Inc.

Inventor： Johannes Solhusvik ,  Kristoffer Ellersgaard Koch ,  Sohrab Yaghmai ,  Jenny Picalausa

IPC: G01R31/28 ,  G11C29/08 ,  G11C29/04 ,  G11C29/26

CPC classification number: G11C29/08 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/2602

Abstract: A method for testing an electronic memory while the memory is in use includes: (a) detecting an access to the electronic memory at a test address, (b) saving, in a register subsystem, write data written to the electronic memory at a location corresponding to the test address, (c) comparing the write data to data read from the electronic memory at the location corresponding to the test address to determine whether the memory has a fault, and (d) generating an error signal if the memory has a fault.

Abstract translation: 一种用于在存储器使用期间测试电子存储器的方法包括：（a）在测试地址处检测对电子存储器的访问，（b）在寄存器子系统中保存在位置处写入电子存储器的写入数据 对应于测试地址，（c）将写入数据与在与测试地址相对应的位置处从电子存储器读取的数据进行比较，以确定存储器是否具有故障，以及（d）如果存储器具有 故障。

公开(公告)号：US20150312537A1

公开(公告)日：2015-10-29

申请号：US14259567

申请日：2014-04-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik ,  Per Olaf Pahr

IPC: H04N9/64 ,  H04N9/04

CPC classification number: H04N9/045 ,  H04N5/343 ,  H04N5/3458 ,  H04N5/347 ,  H04N5/37457 ,  H04N9/04511 ,  H04N2209/045

Abstract: Embodiments of an apparatus including a pixel array including a plurality of individual pixels grouped into pixel kernels having two or more individual pixels, wherein each pixel kernel includes a floating diffusion electrically coupled to all individual pixels in the kernel. A color filter array (CFA) is positioned over and optically coupled to the pixel array, the CFA comprising a plurality of tiled minimal repeating units, each including a plurality of scaled filters having a photoresponse selected from among two or more different photoresponses. Individual pixels within each pixel kernel are optically coupled to a scaled filter. Circuitry and logic coupled to the pixel array cause the apparatus to operate in a first mode wherein signals from a subset of individual pixels are individually transferred to their floating diffusion and read, resulting in a high-resolution, low-sensitivity sub-image and a second mode wherein signals from individual pixels in every pixel kernel are binned into the kernel's floating diffusion and read, resulting in a low-resolution, high-sensitivity image.

Abstract translation: 包括像素阵列的装置的实施例，其包括分组为具有两个或多个单独像素的像素核的多个单独像素，其中每个像素核包括电耦合到所述内核中的所有单独像素的浮动扩散。 滤色器阵列（CFA）位于像素阵列的上方并光学耦合，该CFA包括多个平铺的最小重复单元，每个最小重复单元包括具有选自两个或更多个不同光响应中的光响应的多个缩放滤镜。 每个像素内核中的各个像素光学耦合到缩放滤镜。 耦合到像素阵列的电路和逻辑使得装置以第一模式操作，其中来自各个像素的子集的信号被单独地转移到它们的浮动扩散和读取，导致高分辨率，低灵敏度的子图像和 第二模式，其中来自每个像素核心中的各个像素的信号被分样成内核的浮动扩散和读取，导致低分辨率，高灵敏度的图像。

公开(公告)号：US11451717B2

公开(公告)日：2022-09-20

申请号：US16674964

申请日：2019-11-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Johannes Solhusvik

IPC: H04N5/235 ,  H04N5/3745 ,  H04N5/353 ,  H04N5/355

Abstract: A pixel includes an array of a plurality of photodiodes. The array of photodiodes includes a plurality of rows of photodiodes and a plurality of columns of photodiodes. The plurality of photodiodes includes a set of first photodiodes that has a first surface area and at least one second photodiode that has a second surface area that is smaller than the first surface area. The first photodiodes are arranged to be symmetric with respect to the at least one second photodiode. Output circuitry is electrically coupled to each of the first photodiodes in the set of first photodiodes. A switch is selectively, operably closed to electrically couple the output circuitry to the second photodiode.