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    Image sensor with shared gray code generator and parallel column arithmetic logic units
    2.
    发明授权
    Image sensor with shared gray code generator and parallel column arithmetic logic units 有权

    公开(公告)号：US11431936B2

    公开(公告)日：2022-08-30

    申请号：US16854765

    申请日：2020-04-21

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Min Qu ,  Yu-Shen Yang ,  Charles Qingle Wu

    IPC: H03M1/12 ,  H04N5/378 ,  H03M7/16 ,  H03M1/56 ,  H03K19/21 ,  H03K19/20

    Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

    ARITHMETIC LOGIC UNIT DESIGN IN COLUMN ANALOG TO DIGITAL CONVERTER WITH SHARED GRAY CODE GENERATOR FOR CORRELATED MULTIPLE SAMPLINGS
    3.
    发明申请
    ARITHMETIC LOGIC UNIT DESIGN IN COLUMN ANALOG TO DIGITAL CONVERTER WITH SHARED GRAY CODE GENERATOR FOR CORRELATED MULTIPLE SAMPLINGS 有权

    公开(公告)号：US20220269482A1

    公开(公告)日：2022-08-25

    申请号：US17180520

    申请日：2021-02-19

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Min Qu ,  Chao-Fang Tsai ,  Chun-Hsiang Chang

    IPC: G06F7/507 ,  G06F7/575

    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

    RAMP GENERATOR PROVIDING HIGH RESOLUTION FINE GAIN INCLUDING FRACTIONAL DIVIDER WITH DELTA-SIGMA MODULATOR
    4.
    发明申请
    RAMP GENERATOR PROVIDING HIGH RESOLUTION FINE GAIN INCLUDING FRACTIONAL DIVIDER WITH DELTA-SIGMA MODULATOR 有权

    公开(公告)号：US20210351768A1

    公开(公告)日：2021-11-11

    申请号：US16867399

    申请日：2020-05-05

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Liang Zuo ,  Nijun Jiang ,  Min Qu ,  Xuelian Liu

    IPC: H03K4/06 ,  H03M3/00 ,  H03M1/56 ,  H04N5/378

    Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

    IMAGE SENSOR WITH SHARED GRAY CODE GENERATOR AND PARALLEL COLUMN ARITHMETIC LOGIC UNITS
    6.
    发明申请
    IMAGE SENSOR WITH SHARED GRAY CODE GENERATOR AND PARALLEL COLUMN ARITHMETIC LOGIC UNITS 有权

    公开(公告)号：US20210329185A1

    公开(公告)日：2021-10-21

    申请号：US16854765

    申请日：2020-04-21

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Min Qu ,  Yu-Shen Yang ,  Charles Qingle Wu

    IPC: H04N5/378 ,  H03M7/16 ,  H03M1/56

    Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

    HORIZONTAL BANDING REDUCTION WITH RAMP GENERATOR ISOLATION IN AN IMAGE SENSOR
    7.
    发明申请
    HORIZONTAL BANDING REDUCTION WITH RAMP GENERATOR ISOLATION IN AN IMAGE SENSOR 有权

    公开(公告)号：US20170289470A1

    公开(公告)日：2017-10-05

    申请号：US15087253

    申请日：2016-03-31

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liping Deng ,  Min Qu ,  Bi Yuan ,  Yingkan Lin

    IPC: H04N5/357 ,  H04N5/376 ,  H04N5/378

    CPC classification number: H04N5/357 ,  H04N5/3698 ,  H04N5/37455 ,  H04N5/37457 ,  H04N5/3765 ,  H04N5/378

    Abstract: A readout circuit for use in an image sensor includes a system ramp generator coupled to generate a system ramp signal. A plurality of analog-to-digital converters is coupled to a plurality of column bitlines from a pixel array to receive corresponding analog column image signals. An isolation ramp buffer is coupled between the system ramp generator and the analog-to-digital converters. The isolation ramp buffer includes a single input to receive the system ramp signal, and a plurality of isolated outputs. Each of the isolated outputs is coupled to provide an isolated column ramp signal to a corresponding analog-to-digital converter. Each of the of analog-to-digital converters is coupled to generate a corresponding digital column image signal in response to the corresponding analog column image signal and corresponding isolated column ramp signal.

    Readout circuitry for image sensor
    8.
    发明授权
    Readout circuitry for image sensor 有权
    图像传感器读出电路

    公开(公告)号：US09521348B2

    公开(公告)日：2016-12-13

    申请号：US14696120

    申请日：2015-04-24

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Jie Shen ,  Min Qu ,  Hyunseok Lee

    IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/374

    CPC classification number: H04N5/378 ,  H04N5/374

    Abstract: Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“ADCs”), a plurality of blocks of Static Random-Access Memory (“SRAM”), and a plurality of blocks of Dynamic Random-Access Memory (“DRAM”). The plurality ADCs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels. The plurality of blocks of SRAM is coupled to receive digital image signals from the ADCs. The digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels. The plurality of blocks of DRAM is coupled to the blocks of SRAM. Each block of SRAM is coupled to sequentially output the digital image signals to each of the blocks of DRAM. Each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals.

    Abstract translation: 用于读出图像传感器像素阵列的读出电路包括：读出单元，其包括多个模数转换器（“ADC”），多个静态随机存取存储器块（“SRAM”），以及多个 动态随机存取存储器块（“DRAM”）。 多个ADC耦合到图像传感器像素阵列的读出模拟图像信号二维块。 多个SRAM块被耦合以从ADC接收数字图像信号。 数字图像信号表示从二维像素块读出的模拟图像信号。 DRAM的多个块耦合到SRAM块。 SRAM的每个块被耦合以顺序地将数字图像信号输出到DRAM的每个块。 每个读出单元被耦合以输出数字图像信号作为多个输入/输出（“IO”）信号。

    Analog to digital converter clock control to extend analog gain and reduce noise
    9.
    发明授权
    Analog to digital converter clock control to extend analog gain and reduce noise 有权

    公开(公告)号：US11431939B1

    公开(公告)日：2022-08-30

    申请号：US17217935

    申请日：2021-03-30

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Nijun Jiang ,  Liang Zuo ,  Yuedan Li ,  Min Qu

    IPC: H04N5/378 ,  H03M1/18 ,  H04N5/357 ,  H03M1/12 ,  H03M3/00

    Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

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