Stacked chip shared pixel architecture

    公开(公告)号:US09667895B2

    公开(公告)日:2017-05-30

    申请号:US14707572

    申请日:2015-05-08

    IPC分类号: H04N5/374 H04N5/3745

    CPC分类号: H04N5/37457

    摘要: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

    Negatively charged layer to reduce image memory effect
    6.
    发明授权
    Negatively charged layer to reduce image memory effect 有权
    负电荷层降低图像记忆效应

    公开(公告)号:US09105767B2

    公开(公告)日:2015-08-11

    申请号:US14331652

    申请日:2014-07-15

    摘要: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.

    摘要翻译: 图像传感器像素包括设置在半导体层中的具有第一极性掺杂型的光电二极管区域。 具有第二极性掺杂型的钉扎表面层设置在半导体层中的光电二极管区域的上方。 第一极性电荷层设置在光电二极管区域附近的钉扎表面层附近。 接触蚀刻停止层设置在靠近第一极性电荷层的光电二极管区域的上方。 第一极性电荷层设置在钉扎表面层和接触蚀刻停止层之间,使得第一极性电荷层抵消在接触蚀刻停止层中感应的具有第二极性的电荷。 第一极性电荷层设置在多个钝化层中的第一个和设置在光电二极管区域上的多个钝化层中的第二钝化层之间。

    NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT
    7.
    发明申请
    NEGATIVELY CHARGED LAYER TO REDUCE IMAGE MEMORY EFFECT 有权
    有意义的电荷层减少图像记忆效应

    公开(公告)号:US20140117485A1

    公开(公告)日:2014-05-01

    申请号:US13660774

    申请日:2012-10-25

    IPC分类号: H01L31/0216

    摘要: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.

    摘要翻译: 图像传感器像素包括设置在半导体层中的具有第一极性掺杂型的光电二极管区域。 具有第二极性掺杂型的钉扎表面层设置在半导体层中的光电二极管区域的上方。 第二极性与第一极性相反。 第一极性电荷层设置在光电二极管区域附近的钉扎表面层附近。 接触蚀刻停止层设置在靠近第一极性电荷层的光电二极管区域的上方。 第一极性电荷层设置在钉扎表面层和接触蚀刻停止层之间,使得第一极性电荷层抵消在接触蚀刻停止层中感应的具有第二极性的电荷。 钝化层也设置在钉扎表面层和接触蚀刻停止层之间的光电二极管区域之上。

    Method of fabricating multi-wafer image sensor

    公开(公告)号:US09748308B2

    公开(公告)日:2017-08-29

    申请号:US15166002

    申请日:2016-05-26

    IPC分类号: H01L27/10 H01L27/146

    摘要: A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.

    METHOD OF FABRICATING MULTI-WAFER IMAGE SENSOR
    9.
    发明申请
    METHOD OF FABRICATING MULTI-WAFER IMAGE SENSOR 审中-公开
    制造多波幅图像传感器的方法

    公开(公告)号:US20160268333A1

    公开(公告)日:2016-09-15

    申请号:US15166002

    申请日:2016-05-26

    IPC分类号: H01L27/146

    摘要: A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.

    摘要翻译: 制造图像系统的方法包括形成包括第一半导体衬底和第一互连层的第一晶片。 像素阵列形成在第一半导体衬底的成像区域中,并且第一绝缘填充沟槽形成在第一半导体衬底的外围电路区域中。 此外,形成包括第二半导体衬底和第二互连层的第二晶片。 在第二半导体衬底中形成第二绝缘填充沟槽,并且将第一晶片接合到第二晶片。 第三晶片的第三互连层被结合到第二晶片。 通过第一和第二互连层并穿过第一和第二绝缘填充沟槽形成至少一个深通孔腔。 至少一个深通孔腔被导电材料填充以形成深通孔。