OPTICAL SENSOR WITH SIMULTANEOUS IMAGE/VIDEO AND EVENT DRIVEN SENSING CAPABILITIES

    公开(公告)号:US20220201236A1

    公开(公告)日:2022-06-23

    申请号:US17125630

    申请日:2020-12-17

    Abstract: An optical sensor includes a pixel array of pixel cells. Each pixel cell includes photodiodes to photogenerate charge in response to incident light and a source follower to generate an image data signal in response to the charge photogenerated from the photodiodes. An image readout circuit is coupled to the pixel cells to read out the image data signal generated from the source follower of at least one of the pixel cells of a row of the pixel array. An event driven circuit is coupled to the pixel cells to read out the event data signals generated in response to the charge from the photodiodes of another row of the pixel cells of the pixel array. The image readout circuit is coupled to read out the image data signal and the event driven circuit is coupled to read out the event data signals from pixel array simultaneously.

    Switching techniques for fast voltage settling in image sensors

    公开(公告)号:US11252346B1

    公开(公告)日:2022-02-15

    申请号:US17037282

    申请日:2020-09-29

    Abstract: Switching techniques for fast voltage settling in image sensors are described. In one embodiment, a transfer gate (TX) driver circuit of an image sensor includes a TX driver configured to provide a TX driver voltage to a plurality of pixels of an image sensor. A power supply (NVDD) is operationally coupled to the TX driver. A first switch (SW1) operationally coupling an outside capacitance (Cext) and the TX driver. A second switch (SW2) operationally coupling the Cext and the NVDD. A third switch (SW3) operationally coupling the NVDD and the TX driver. A falling edge of the TX driver voltage is configured to control a start of data transfer from individual pixels of the plurality of pixels. The SW1 and the SW2 are configured in an open position before the falling edge of the TX driver voltage. The SW3 is configured in a closed position before the falling edge.

    High dynamic range CMOS image sensor design

    公开(公告)号:US11212457B2

    公开(公告)日:2021-12-28

    申请号:US16886473

    申请日:2020-05-28

    Abstract: A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

    Dual conversion gain high dynamic range image sensor readout circuit memory storage structure

    公开(公告)号:US10432879B2

    公开(公告)日:2019-10-01

    申请号:US15872741

    申请日:2018-01-16

    Abstract: A readout circuit includes a comparator coupled to receive a ramp signal an output of a dual conversion gain pixel. A single counter is coupled to the output of the comparator. The counter is coupled to write to only one of a first or a second memory circuits at a time. A first multiplexor is coupled to load either an initial value or an initial memory value from the first memory circuit into the counter. A second multiplexor is coupled to load either a low conversion gain memory value from the first memory circuit or a high conversion gain memory value from the second memory circuit into a single data transmitter, which is coupled to transmit the received memory value to a digital processor.

    CAPMID design in VRFD for HDR structure

    公开(公告)号:US12294801B2

    公开(公告)日:2025-05-06

    申请号:US18303479

    申请日:2023-04-19

    Abstract: A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

    SAMPLE AND HOLD SWITCH DRIVER CIRCUITRY WITH SLOPE CONTROL

    公开(公告)号:US20220078360A1

    公开(公告)日:2022-03-10

    申请号:US17530316

    申请日:2021-11-18

    Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

    Hybrid CMOS image sensor with event driven sensing

    公开(公告)号:US11240454B2

    公开(公告)日:2022-02-01

    申请号:US16862337

    申请日:2020-04-29

    Inventor: Zhe Gao Tiejun Dai

    Abstract: An image sensor includes a source follower coupled to a photodiode to generate an image signal responsive to photogenerated charge. The image signal is received by image readout circuitry through a row select transistor. A reset transistor resets the photogenerated charge. A first node of mode select circuit is coupled to the reset transistor, a second node is coupled to a pixel supply voltage, and a third node is coupled to an event driven circuit. The mode select circuit couples the first node to the second node during an imaging mode to supply the pixel supply voltage to the reset transistor. The mode select circuit is further configured to couple the first node to the third node during an event driven mode to couple a photocurrent of the photodiode to drive the event driven circuit through the reset transistor to detect changes in the photocurrent.

    Sample and hold switch driver circuitry with slope control

    公开(公告)号:US11212467B2

    公开(公告)日:2021-12-28

    申请号:US16516067

    申请日:2019-07-18

    Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

    High dynamic range high speed CMOS image sensor design

    公开(公告)号:US11140352B1

    公开(公告)日:2021-10-05

    申请号:US17121423

    申请日:2020-12-14

    Abstract: A readout circuit for use in an image sensor includes a first sample and hold (SH) circuit coupled to a bitline that is coupled to a pixel array. A second SH circuit is coupled to the bitline. A bypass switch is coupled to the bitline, the first SH circuit, and the second SH circuit. An analog to digital converter (ADC) is coupled to the bypass switch. The bypass switch is configured to provide an image charge value from the pixel array to the ADC through the bitline, or through one of the first SH circuit or the second SH circuit in response to a switch select signal.

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