公开(公告)号：US11750950B1

公开(公告)日：2023-09-05

申请号：US17804238

申请日：2022-05-26

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Ling Fu ,  Tiejun Dai ,  Zhe Gao

IPC: H04N25/75 ,  H01L27/146 ,  H04N25/77 ,  H04N25/531 ,  H04N25/532

CPC classification number: H04N25/75 ,  H01L27/14612 ,  H04N25/531 ,  H04N25/77

Abstract: A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

公开(公告)号：US20210377435A1

公开(公告)日：2021-12-02

申请号：US16886473

申请日：2020-05-28

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Keiji Mabuchi ,  Zhe Gao

IPC: H04N5/235 ,  H01L27/092 ,  H04N5/345 ,  H01L27/146

Abstract: A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

公开(公告)号：US10547804B2

公开(公告)日：2020-01-28

申请号：US15291917

申请日：2016-10-12

Applicant: OmniVision Technologies, Inc.

Inventor： Tiejun Dai ,  Jing Yin ,  Rui Wang

IPC: H04N3/14 ,  H04N5/235 ,  H04N5/365 ,  H04N5/378 ,  H04N5/357 ,  H04N5/3745 ,  H04N5/369

Abstract: Systems and methods for fixed pattern noise reduction in image sensors is disclosed herein. An example method may include simultaneously providing a pixel reference voltage of a pixel to a reference sampling capacitor and a signal sampling capacitor, decoupling the reference sampling capacitor from the pixel, providing a signal voltage to the signal sampling capacitor, and decoupling the signal sampling capacitor from the pixel.

公开(公告)号：US10375338B2

公开(公告)日：2019-08-06

申请号：US15421881

申请日：2017-02-01

Applicant: OmniVision Technologies, Inc.

Inventor： Zheng Yang ,  Hiroaki Ebihara ,  Chun-Ming Tang ,  Chao-Fang Tsai ,  Rui Wang ,  Tiejun Dai

IPC: H04N5/378 ,  H04N5/369 ,  H04N5/374 ,  H01L27/146 ,  H04N5/3745

Abstract: A hybrid bonded image sensor has a photodiode die with macrocells having at least one photodiode and a bond contact; a supporting circuitry die with multiple supercells, each supercell having at least one macrocell unit having a bond contact coupled to the bond contact of a macrocell of the photodiode die. Each macrocell unit lies within a supercell and has a reset transistor adapted to reset photodiodes of the macrocell of the photodiode die. Each supercell has at least one common source amplifier adapted to receive signal from the bond contact of a selected macrocell unit of the supercell, the common source amplifier coupled to drive a column line through a selectable source follower. In embodiments, the common source amplifiers of several supercells drive the selectable source follower through a distributed differential amplifier.

公开(公告)号：US20180255255A1

公开(公告)日：2018-09-06

申请号：US15446711

申请日：2017-03-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Yingkan Lin ,  Tiejun Dai ,  Cheng-Pin Lin ,  Yu-Shen Yang

IPC: H04N5/357 ,  H04N5/376 ,  H04N5/907 ,  H04N5/378

CPC classification number: H04N5/3577 ,  H04N5/3765 ,  H04N5/378 ,  H04N5/907

Abstract: Methods and apparatuses for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.

公开(公告)号：US09608027B2

公开(公告)日：2017-03-28

申请号：US14624198

申请日：2015-02-17

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tianjia Sun ,  Rui Wang ,  Tiejun Dai

IPC: H01L27/14 ,  H01L27/146 ,  G01S17/89 ,  G01S17/02 ,  G01S7/481 ,  G01S7/491 ,  H04N9/04

CPC classification number: H01L27/14647 ,  G01S7/4816 ,  G01S7/4914 ,  G01S17/023 ,  G01S17/89 ,  H01L27/14634 ,  H01L27/14645 ,  H01L27/14652 ,  H04N9/045

Abstract: A pixel array includes a plurality of visible light pixels arranged in the pixel array. Each one of the plurality of visible light pixels includes a photosensitive element arranged in a first semiconductor die to detect visible light. Each one of the plurality of visible light pixels is coupled to provide color image data to visible light readout circuitry disposed in a second semiconductor die stacked with and coupled to the first semiconductor die in a stacked chip scheme. A plurality of infrared (IR) pixels arranged in the pixel array. Each one of the plurality of IR pixels includes a single photon avalanche photodiode (SPAD) arranged in the first semiconductor die to detect IR light. Each one of the plurality of visible light pixels is coupled to provide IR image data to IR light readout circuitry disposed in the second semiconductor die.

公开(公告)号：US20160353084A1

公开(公告)日：2016-12-01

申请号：US14721424

申请日：2015-05-26

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tianjia Sun ,  Rui Wang ,  Tiejun Dai

IPC: H04N13/02 ,  H04N5/374 ,  G01S7/486 ,  G06T7/00

CPC classification number: H04N13/254 ,  G01S7/4816 ,  G01S7/4863 ,  G01S7/4865 ,  G01S7/497 ,  G01S17/89 ,  H01L27/14609 ,  H01L27/14627 ,  H01L27/14634 ,  H04N5/374 ,  H04N13/211 ,  H04N2013/0081

Abstract: A time of flight sensor includes control circuitry and a time of flight pixel array. The control circuitry is coupled to synchronously send a sync signal. The time of flight pixel array includes a plurality of time of flight pixel cells. Each one of the time of flight pixel cells includes a photosensor and a delay circuit. The photosensor is configured to generate an image signal in response to receiving photons from a light pulse reflected from an object. The delay circuit is coupled to generate a delayed sync signal in response to the sync signal. The delay circuit includes a delay transistor. The time of flight pixel array includes a transistor gradient where a transistor gate length of the delay transistor varies so that each of the time of flight pixel cells receive their respective delayed sync signal at a same time.

Abstract translation: 飞行时间传感器包括控制电路和飞行时间像素阵列。 控制电路被耦合以同步地发送同步信号。 飞行时间像素阵列包括多个飞行时间像素单元。 飞行时间像素单元中的每一个包括光电传感器和延迟电路。 光传感器被配置为响应于从对象反射的光脉冲接收光子而产生图像信号。 延迟电路被耦合以响应于同步信号产生延迟的同步信号。 延迟电路包括延迟晶体管。 飞行时间像素阵列包括晶体管梯度，其中延迟晶体管的晶体管栅极长度变化，使得每个飞行时间像素单元同时接收它们各自的延迟同步信号。

公开(公告)号：US09478579B2

公开(公告)日：2016-10-25

申请号：US14033293

申请日：2013-09-20

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Guannho George Tsau

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464

Abstract: An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.

Abstract translation: 示例性成像传感器系统包括形成在第一晶片的第一半导体层中的背面照明CMOS成像阵列。 CMOS成像阵列包括N个像素，其中每个像素包括光电二极管区域。 第一晶片在第一晶片的第一金属堆叠和第二晶片的第二金属堆叠之间的结合界面处结合到第二晶片。 存储装置设置在第二晶片的第二半导体层中。 存储装置包括至少N个存储单元，其中N个存储单元中的每一个被配置为存储表示由相应光电二极管区域累积的图像电荷的信号。 每个存储单元包括对光诱导的泄漏敏感的电路元件。

公开(公告)号：US09332193B2

公开(公告)日：2016-05-03

申请号：US14253699

申请日：2014-04-15

Applicant: OmniVision Technologies, Inc.

Inventor： Tiejun Dai ,  Junzhao Lei

IPC: H04N5/235 ,  H01L27/146 ,  H04N5/353 ,  H04N5/225

CPC classification number: H04N5/2354 ,  H01L27/14601 ,  H04N5/3532 ,  H04N2005/2255

Abstract: A multiple image sensor image acquisition system includes a clock control unit to generate a synchronization clock signal. The synchronization clock signal has a prolonged constant cycle during which the synchronization clock signal is held at a constant level for a period of time corresponding to multiple clock cycles. A first image sensor is coupled with the clock control unit to receive the synchronization clock signal and has a first synchronization unit that is operable to synchronize operation for the first image sensor based on detection of an end of the prolonged constant cycle. A second image sensor is coupled with the clock control unit to receive the synchronization clock signal and has a second synchronization unit that is operable to synchronize operation for the second image sensor based on detection of the end of the prolonged constant cycle. The image sensors are synchronized operationally.

Abstract translation: 多图像传感器图像采集系统包括产生同步时钟信号的时钟控制单元。 同步时钟信号具有延长的恒定周期，在此期间同步时钟信号在对应于多个时钟周期的时间段内保持在恒定电平。 第一图像传感器与时钟控制单元耦合以接收同步时钟信号，并且具有第一同步单元，其可操作以基于对延长的恒定周期的结束的检测来同步第一图像传感器的操作。 第二图像传感器与时钟控制单元耦合以接收同步时钟信号，并且具有第二同步单元，其可操作以基于延长的恒定周期的结束的检测来同步第二图像传感器的操作。 图像传感器在操作上是同步的。

公开(公告)号：US20160037111A1

公开(公告)日：2016-02-04

申请号：US14448154

申请日：2014-07-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Rui Wang ,  Dyson H. Tai ,  Sohei Manabe

IPC: H04N5/378 ,  H01L27/146 ,  H04N5/376

CPC classification number: H04N5/378 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/14636 ,  H04N5/376

Abstract: A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.

Abstract translation: 像素单元包括设置在第一半导体芯片内的光电二极管，用于响应入射在光电二极管上的光累积图像电荷。 传输晶体管设置在第一半导体芯片内并耦合到光电二极管以从光电二极管传输图像电荷。 偏置电压产生电路，设置在第二半导体芯片内，用于产生偏置电压。 偏置电压产生电路耦合到第一半导体芯片以偏置偏压的光电二极管。 偏置电压相对于第二半导体芯片的接地电压为负。 浮置扩散部设置在第二半导体芯片内。 传输晶体管被耦合以将图像电荷从第一半导体芯片上的光电二极管转移到第二半导体芯片上的浮动扩散。