Voltage domain global shutter readout circuit timing

    公开(公告)号:US11750950B1

    公开(公告)日:2023-09-05

    申请号:US17804238

    申请日:2022-05-26

    CPC classification number: H04N25/75 H01L27/14612 H04N25/531 H04N25/77

    Abstract: A global shutter readout circuit includes a pixel enable signal and a first sample and hold (SH) signal that are configured to turn ON a pixel enable transistor and a first storage transistor at a first time during a global transfer period. The pixel enable signal is configured to begin a transition to an OFF level at a second time and complete the transition to the OFF level at a third time to turn OFF the pixel enable transistor. The first SH signal is configured to begin a transition to the OFF level at a fourth time, which occurs after the second and third times, and complete the transition to the OFF level at a fifth time to turn OFF the first storage transistor. An OFF transition duration between the fourth and fifth times is greater than an ON transition duration of the first SH signal at the first time.

    HIGH DYNAMIC RANGE CMOS IMAGE SENSOR DESIGN

    公开(公告)号:US20210377435A1

    公开(公告)日:2021-12-02

    申请号:US16886473

    申请日:2020-05-28

    Abstract: A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

    Real GS and OFG timing design for 1-by-2 shared HDR VDGS

    公开(公告)号:US12200388B2

    公开(公告)日:2025-01-14

    申请号:US18313957

    申请日:2023-05-08

    Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

    REAL GS AND OFG TIMING DESIGN FOR 1-BY-2 SHARED HDR VDGS

    公开(公告)号:US20240381002A1

    公开(公告)日:2024-11-14

    申请号:US18313957

    申请日:2023-05-08

    Abstract: An imaging system includes a pixel array with odd and even pixel cells. Each of the odd and even pixel cells includes a photodiode, a floating diffusion, a transfer transistor, a reset transistor, a lateral overflow integration capacitor (LOFIC), and an overflow gate (OFG) transistor. The imaging system further includes a readout circuit with a sample and hold (SH) circuit and an analog to digital converter. The OFG transistor of each of the odd and even pixel cells is configured to direct the image charge photogenerated by the respective photodiode away from the respective transfer transistor and reduce photodiode exposure shift during LOFIC readouts during a global transfer period.

    Digital time stamping design for event driven pixel

    公开(公告)号:US11516419B2

    公开(公告)日:2022-11-29

    申请号:US17156290

    申请日:2021-01-22

    Abstract: An event driven pixel includes a photodiode configured to photogenerate charge in response to incident light received from an external scene. A photocurrent to voltage converter is coupled to the photodiode to convert photocurrent generated by the photodiode to a voltage. A filter amplifier is coupled to the photocurrent to voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent to voltage converter. A threshold comparison stage is coupled to the filter amplifier to compare the filtered and amplified signal received from the filter amplifier with thresholds to asynchronously detect events in the external scene in response to the incident light. A digital time stamp generator is coupled to asynchronously generate a digital time stamp in response to the events asynchronously detected in the external scene by the threshold comparison stage.

    AUTO-ZERO TECHNIQUES FOR LATERAL OVERFLOW INTEGRATING CAPACITOR (LOFIC) READOUT IMAGE SENSOR

    公开(公告)号:US20220159206A1

    公开(公告)日:2022-05-19

    申请号:US17098230

    申请日:2020-11-13

    Inventor: Zhe Gao Tiejun Dai

    Abstract: Switching techniques for fast voltage settling in image sensors are described. In one embodiment, an image sensor includes a plurality of lateral overflow integrating capacitor (LOFIC) pixels arranged in rows and columns of a pixel array. The plurality of pixels includes an active pixel configured for exposure to light, and a dummy pixel at least partially protected from exposure to light. A common bitline (BL) is couplable to the active pixel and the dummy pixel. A comparator (OA1) is coupled to the bitline. The comparator is configured to receive a pixel voltage (Vx) from the active pixel on one input and a ramp voltage (Vy) on another input. Charge accumulated by the active pixel is determined at least in part by an intersection between the ramp voltage and the pixel voltage.

    CAPMID DESIGN IN VRFD FOR HDR STRUCTURE
    7.
    发明公开

    公开(公告)号:US20240357253A1

    公开(公告)日:2024-10-24

    申请号:US18303479

    申请日:2023-04-19

    CPC classification number: H04N25/77 H04N25/78

    Abstract: A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

    Event driven pixel for spatial information extraction

    公开(公告)号:US11430828B2

    公开(公告)日:2022-08-30

    申请号:US17125619

    申请日:2020-12-17

    Abstract: An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

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