公开(公告)号：US10983921B2

公开(公告)日：2021-04-20

申请号：US16780822

申请日：2020-02-03

Applicant: Oracle International Corporation

Inventor： John Feehrer ,  Patrick Stabile ,  Gregory Onufer ,  John Johnson

IPC: G06F12/1081 ,  G06F3/06 ,  G06F13/28

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

公开(公告)号：US20200174946A1

公开(公告)日：2020-06-04

申请号：US16780822

申请日：2020-02-03

Applicant: Oracle International Corporation

Inventor： John Feehrer ,  Patrick Stabile ,  Gregory Onufer ,  John Johnson

IPC: G06F12/1081 ,  G06F3/06 ,  G06F13/28

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

公开(公告)号：US20170293539A1

公开(公告)日：2017-10-12

申请号：US15632567

申请日：2017-06-26

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F11/20 ,  G06F9/30 ,  G06F3/06

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.