Implementation of reset functions in an SoC virtualized device

    公开(公告)号:US10296356B2

    公开(公告)日:2019-05-21

    申请号:US14944893

    申请日:2015-11-18

    Abstract: An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.

    Input/output direct memory access during live memory relocation

    公开(公告)号:US10983921B2

    公开(公告)日:2021-04-20

    申请号:US16780822

    申请日:2020-02-03

    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

    INPUT/OUTPUT DIRECT MEMORY ACCESS DURING LIVE MEMORY RELOCATION

    公开(公告)号:US20200174946A1

    公开(公告)日:2020-06-04

    申请号:US16780822

    申请日:2020-02-03

    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

    Input/output direct memory access during live memory relocation

    公开(公告)号:US10552340B2

    公开(公告)日:2020-02-04

    申请号:US15444795

    申请日:2017-02-28

    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

    Separation of control and data plane functions in SoC virtualized I/O device

    公开(公告)号:US10853303B2

    公开(公告)日:2020-12-01

    申请号:US14944835

    申请日:2015-11-18

    Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

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