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公开(公告)号：US09280290B2
公开(公告)日：2016-03-08
申请号：US14178626
申请日：2014-02-12
Applicant: Oracle International Corporation
Inventor： John R Feehrer , Hugh R Kurth , Aron J Silverton , Patrick Stabile
CPC classification number: G06F3/061 , G06F3/0635 , G06F3/0673 , G06F13/28 , G06F13/4027
Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.
Abstract translation: 系统可以包括处理器，其可以包括高速缓冲存储器和直接存储器访问（DMA）控制器，I / O扩展总线上的外围设备以及耦合到I / O扩展总线和处理器的总线接口。 总线控制器可以确定从外围设备发送到处理器的数据分组是否包括具有可选期望高速缓存位置的高速缓存存储器的DMA写指令。 在确定对高速缓存存储器的DMA写指令被包括在数据分组中时，总线控制器可以格式化数据分组中的数据以存储在高速缓存中，并且接收所需的高速缓存位置或者确定缓存内的适当位置以存储 格式化数据。 如果高速缓存内的期望位置不能接收来自外围设备的更多数据，则总线控制器可以确定高速缓存内的替换位置。
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公开(公告)号：US09952989B2
公开(公告)日：2018-04-24
申请号：US15277146
申请日：2016-09-27
Applicant: Oracle International Corporation
Inventor： John R. Feehrer , Patrick Stabile , Hugh R. Kurth , David M. Kahn
CPC classification number: G06F13/24 , G06F13/16 , G06F13/1605 , G06F13/4068
Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.
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公开(公告)号：US20150356036A1
公开(公告)日：2015-12-10
申请号：US14300388
申请日：2014-06-10
Applicant: Oracle International Corporation
Inventor： John R Feehrer , Patrick Stabile , Hugh R Kurth , David M Kahn
CPC classification number: G06F13/24 , G06F13/16 , G06F13/1605 , G06F13/4068
Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.
Abstract translation: 公开了输入/输出集线器单元的实施例，用于聚合从多个端点设备接收的中断。 输入/输出集线器可以包括接口单元和一个或多个通信单元。 每个通信单元可以被配置为从相应的端点设备接收消息。 接口单元可以被配置为响应于来自给定的一个通信单元的请求来更新第一数据结构内的第一指针。 接口单元还可以被配置为响应于更新第一指针，读取第二指针和第一指针而响应于第一和第二指针相等的确定发送中断，将数据存储在第二数据结构中。
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公开(公告)号：US20170017589A1
公开(公告)日：2017-01-19
申请号：US15277146
申请日：2016-09-27
Applicant: Oracle International Corporation
Inventor： John R. Feehrer , Patrick Stabile , Hugh R. Kurth , David M. Kahn
CPC classification number: G06F13/24 , G06F13/16 , G06F13/1605 , G06F13/4068
Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.
Abstract translation: 公开了输入/输出集线器单元的实施例，用于聚合从多个端点设备接收的中断。 输入/输出集线器可以包括接口单元和一个或多个通信单元。 每个通信单元可以被配置为从相应的端点设备接收消息。 接口单元可以被配置为响应于来自给定的一个通信单元的请求来更新第一数据结构内的第一指针。 接口单元还可以被配置为响应于更新第一指针，读取第二指针和第一指针而响应于第一和第二指针相等的确定发送中断，将数据存储在第二数据结构中。
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公开(公告)号：US09396142B2
公开(公告)日：2016-07-19
申请号：US14300418
申请日：2014-06-10
Applicant: Oracle International Corporation
Inventor： John R Feehrer , Patrick Stabile , Hugh R Kurth , David M Kahn , Robert Dickson
CPC classification number: G06F13/32 , G06F9/45533 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F12/1063
Abstract: An input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrupts or messages from a corresponding endpoint device. A given communication unit may be further configured to synthesize a virtual address from the received message, translate the synthesized virtual address to a real address, and then translate the real address to a physical address. The interface unit may be configured to send an interrupt dependent upon the physical address.
Abstract translation: 输入/输出集线器可以包括接口单元和一个或多个通信单元。 每个通信单元可以被配置为从相应的端点设备接收中断或消息。 给定通信单元还可以被配置为从接收到的消息中合成虚拟地址，将合成的虚拟地址转换成真实地址，然后将实际地址转换为物理地址。 接口单元可以被配置为发送取决于物理地址的中断。
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Patent Agency Ranking
公开(公告)号：US10983921B2
公开(公告)日：2021-04-20
申请号：US16780822
申请日：2020-02-03
Applicant: Oracle International Corporation
Inventor： John Feehrer , Patrick Stabile , Gregory Onufer , John Johnson
IPC: G06F12/1081 , G06F3/06 , G06F13/28
Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.
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公开(公告)号：US20200174946A1
公开(公告)日：2020-06-04
申请号：US16780822
申请日：2020-02-03
Applicant: Oracle International Corporation
Inventor： John Feehrer , Patrick Stabile , Gregory Onufer , John Johnson
IPC: G06F12/1081 , G06F3/06 , G06F13/28
Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.
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公开(公告)号：US09507740B2
公开(公告)日：2016-11-29
申请号：US14300388
申请日：2014-06-10
Applicant: Oracle International Corporation
Inventor： John R Feehrer , Patrick Stabile , Hugh R Kurth , David M Kahn
CPC classification number: G06F13/24 , G06F13/16 , G06F13/1605 , G06F13/4068
Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.
Abstract translation: 公开了输入/输出集线器单元的实施例，用于聚合从多个端点设备接收的中断。 输入/输出集线器可以包括接口单元和一个或多个通信单元。 每个通信单元可以被配置为从相应的端点设备接收消息。 接口单元可以被配置为响应于来自给定的一个通信单元的请求来更新第一数据结构内的第一指针。 接口单元还可以被配置为响应于更新第一指针，读取第二指针和第一指针而响应于第一和第二指针相等的确定发送中断，将数据存储在第二数据结构中。
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公开(公告)号：US20150227312A1
公开(公告)日：2015-08-13
申请号：US14178626
申请日：2014-02-12
Applicant: Oracle International Corporation
Inventor： John R. Feehrer , Hugh R. Kurth , Aron J. Silverton , Patrick Stabile
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0635 , G06F3/0673 , G06F13/28 , G06F13/4027
Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.
Abstract translation: 系统可以包括处理器，其可以包括高速缓冲存储器和直接存储器访问（DMA）控制器，I / O扩展总线上的外围设备以及耦合到I / O扩展总线和处理器的总线接口。 总线控制器可以确定从外围设备发送到处理器的数据分组是否包括具有可选期望高速缓存位置的高速缓存存储器的DMA写指令。 在确定对高速缓存存储器的DMA写指令被包括在数据分组中时，总线控制器可以格式化数据分组中的数据以存储在高速缓存中，并且接收所需的高速缓存位置或者确定缓存内的适当位置以存储 格式化数据。 如果高速缓存内的期望位置不能接收来自外围设备的更多数据，则总线控制器可以确定高速缓存内的替换位置。
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公开(公告)号：US10552340B2
公开(公告)日：2020-02-04
申请号：US15444795
申请日：2017-02-28
Applicant: Oracle International Corporation
Inventor： John Feehrer , Patrick Stabile , Gregory Onufer , John Johnson
IPC: G06F12/1081 , G06F3/06 , G06F13/28
Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.
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