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    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    1.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 有权

    公开(公告)号：US20220156075A1

    公开(公告)日：2022-05-19

    申请号：US17648443

    申请日：2022-02-02

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    5.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 有权
    将CPU状态从不可操作的核心迁移到备用核心的方法

    公开(公告)号：US20160147534A1

    公开(公告)日：2016-05-26

    申请号：US14549742

    申请日：2014-11-21

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F9/30 ,  G06F12/08

    CPC classification number: G06F9/30145 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/2028 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/13

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

    Abstract translation: 公开了一种装置，其中装置可以包括多个芯，包括第一芯，第二芯和第三芯，以及耦合到第一芯的电路。 第一核可以被配置为处理多个指令。 电路可以被配置为检测第一核心停止提交多个指令的子集，并且向第二核心发送指示第一核心停止提交子集的指示。 第二核心可以被配置为响应于接收到指示而禁止第一核心进一步处理该子集的指令，并且响应于禁用第一核心将数据从第一核心复制到第三核心。 第三核可以被配置为依赖于数据来恢复处理该子集。

    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    7.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 审中-公开

    公开(公告)号：US20200210185A1

    公开(公告)日：2020-07-02

    申请号：US16735564

    申请日：2020-01-06

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

    Input/output direct memory access during live memory relocation
    8.
    发明授权
    Input/output direct memory access during live memory relocation 有权

    公开(公告)号：US10552340B2

    公开(公告)日：2020-02-04

    申请号：US15444795

    申请日：2017-02-28

    Applicant: Oracle International Corporation

    Inventor： John Feehrer ,  Patrick Stabile ,  Gregory Onufer ,  John Johnson

    IPC: G06F12/1081 ,  G06F3/06 ,  G06F13/28

    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

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