公开(公告)号：US20240380919A1

公开(公告)日：2024-11-14

申请号：US18779516

申请日：2024-07-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20240373046A1

公开(公告)日：2024-11-07

申请号：US18775630

申请日：2024-07-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/30 ,  H04N19/103 ,  H04N19/157 ,  H04N19/169 ,  H04N19/70

Abstract: An encoder includes: memory; and circuitry coupled to the memory and configured to generate an encoded bitstream. In the encoder, when a multi-layer structure is to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream (i) a sequence parameter set that refers to a video parameter set and (ii) a network abstraction layer (NAL) unit having a layer identification (ID) greater than zero in the multi-layer structure, and when the multi-layer structure is not to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream a sequence parameter set that does not refer to the video parameter set.

公开(公告)号：US20240373023A1

公开(公告)日：2024-11-07

申请号：US18773863

申请日：2024-07-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/126 ,  H04N19/159 ,  H04N19/176 ,  H04N19/61

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry, in which the circuitry: derives a prediction residual indicating a difference between a current block and a prediction image of the current block; performs primary transform on the prediction residual, and performs secondary transform on a result of the primary transform; performs quantization on a result of the secondary transform; and encodes a result of the quantization. In the performing of the secondary transform, when a matrix weighted intra prediction included in intra prediction and having prediction modes is used, the circuitry uses, as a transform set for the secondary transform, a common transform set shared among the prediction modes. The matrix weighted intra prediction generates the prediction image by performing matrix calculation on a pixel sequence obtained from pixel values of surrounding pixels of the current block.

公开(公告)号：US20240364880A1

公开(公告)日：2024-10-31

申请号：US18764812

申请日：2024-07-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

Abstract: Various embodiments provide a decoder configured to select a filter based on a block size of a first block and a block size of a second block in an image, and change values of pixels in the first block and the second block. The filter includes a first set of multipliers and a first set of offsets for the first block, and a second set of multipliers and a second set of offsets for the second block. The values of the pixels in the first block and the second block are changed by performing multiplication with each multiplier in the first set of multipliers, by performing multiplication with each multiplier in the second set of multipliers, and by using the first set of offsets and the second set of offsets.

公开(公告)号：US20240259551A1

公开(公告)日：2024-08-01

申请号：US18606492

申请日：2024-03-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/103 ,  H04N19/186 ,  H04N19/60 ,  H04N19/70

CPC classification number: H04N19/103 ,  H04N19/186 ,  H04N19/60 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: determines whether an image format of a video is a format including a chroma component; when it is determined that the image format is a format including a chroma component, signals a flag indicating whether application of JCCR is allowed or not in a header of a stream, and (i) encodes the video with application of the JCCR allowed, or (ii) encodes the video with application of the JCCR not allowed; and when it is determined that the image format is a format including no chroma component, signals no flag indicating whether application of the JCCR is allowed or not in the header of the stream, and encodes the video with application of the JCCR not allowed.

公开(公告)号：US20240196005A1

公开(公告)日：2024-06-13

申请号：US18586227

申请日：2024-02-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/537 ,  H04N19/119 ,  H04N19/176

CPC classification number: H04N19/537 ,  H04N19/119 ,  H04N19/176

Abstract: An encoder, when sub-block encoding is to be performed, determines a plurality of sub-blocks in a first image block, the plurality of sub-blocks including a first sub-block, determines a first motion vector for the first sub-block by referring to a first candidate list, performs first inter prediction processing on the first sub-block using the first motion vector, and encodes the first image block using a result of the first inter prediction processing. When partition encoding is to be performed, the encoder, in operation, determines a plurality of partitions in a second image block, the plurality of partitions including a first partition, determines a second motion vector for the first partition by referring to a second candidate list, performs second inter prediction processing on the first partition using the second motion vector, and encodes the second image block using a result of the second inter prediction processing.

公开(公告)号：US20240163431A1

公开(公告)日：2024-05-16

申请号：US18417952

申请日：2024-01-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US20240089493A1

公开(公告)日：2024-03-14

申请号：US18514809

申请日：2023-11-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI

IPC: H04N19/52 ,  H04N19/12 ,  H04N19/174 ,  H04N19/182

CPC classification number: H04N19/52 ,  H04N19/12 ,  H04N19/174 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: corrects a base motion vector using a correction value for correcting the base motion vector in a predetermined direction; and encodes a current partition to be encoded in an image of a video, using the base motion vector corrected. The correction value is specified by a first parameter and a second parameter, the first parameter indicating a table to be selected from among a plurality of tables each including values, the second parameter indicating one of the values included in the table to be selected indicated by the first parameter. In each of the plurality of tables, a smaller value among the values is assigned a smaller index. Each of the plurality of tables includes a different minimum value among the values.

公开(公告)号：US20240089479A1

公开(公告)日：2024-03-14

申请号：US18510430

申请日：2023-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Han Boon TEO ,  Takahiro NISHI ,  Ryuichi KANOH ,  Tadamasa TOMA

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176

Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.

公开(公告)号：US20230396763A1

公开(公告)日：2023-12-07

申请号：US18365054

申请日：2023-08-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Ru Ling LIAO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/60 ,  H04N19/50 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/60 ,  H04N19/50 ,  H04N19/176

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.