公开(公告)号：US08806090B2

公开(公告)日：2014-08-12

申请号：US13149457

申请日：2011-05-31

申请人： Douglas A. Larson ,  Joseph M. Jeddeloh

发明人： Douglas A. Larson ,  Joseph M. Jeddeloh

IPC分类号： G06F3/00 ,  G06F12/02 ,  H04L12/56

CPC分类号： G06F5/14 ,  G06F12/023 ,  G06F12/0246 ,  G06F13/28 ,  G06F2205/126 ,  G06F2212/7201 ,  G11C7/10 ,  G11C16/06 ,  H04L49/901

摘要： Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

摘要翻译： 存储器系统控制器可以包括硬件主器件，第一缓冲器和耦合到硬件主器件和第一缓冲器的开关。 交换机可以包括第二缓冲器和缓冲器分配管理（BAM）电路。 BAM电路可以包括缓冲标签池。 缓冲标签池可以包括标签，每个标签标识相应的第一缓冲器或相应的第二缓冲器。 BAM电路可以被配置为响应于来自硬件主机的分配请求而向硬件主机分配标签。 可以将BAM电路配置为优先于识别标识第一缓冲器的标签上标识第二缓冲器的标签的分配。

公开(公告)号：US08555006B2

公开(公告)日：2013-10-08

申请号：US13301653

申请日：2011-11-21

申请人： Joseph M. Jeddeloh ,  Ralph James

发明人： Joseph M. Jeddeloh ,  Ralph James

IPC分类号： G06F12/00

CPC分类号： G06F13/1642 ,  G06F13/1605 ,  G06F13/1684

摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

公开(公告)号：US08448018B2

公开(公告)日：2013-05-21

申请号：US13605124

申请日：2012-09-06

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F11/16

CPC分类号： G06F11/08 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1028 ,  G06F11/108

摘要： The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

摘要翻译： 本公开包括用于基于条带的存储器操作的方法和设备。 一种方法实施例包括在多个存储器件的存储卷上写入第一条带中的数据。 通过在多个存储器件的存储卷上的第二条带的一部分中写入更新的数据来更新第一条带的一部分。 第一条纹的部分无效。 第一条纹的无效部分和第一条纹的剩余部分被保持直到第一条带被回收。 还公开了其它方法和装置。

公开(公告)号：US20120303885A1

公开(公告)日：2012-11-29

申请号：US13568447

申请日：2012-08-07

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G11C5/00 ,  G06F12/0862 ,  G06F13/4022

摘要： A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

摘要翻译： 基于处理器的电子系统包括布置在第一和第二等级中的几个存储器模块。 第一级的存储器模块由几个处理器中的任何一个直接访问，并且第二级的存储器模块由处理器通过第一级的存储器模块访问。 通过改变用于访问第二组中的存储器模块的第一级中的存储器模块的数量来改变处理器和第二级中的存储器模块之间的数据带宽。 每个存储器模块包括耦合到存储器集线器的多个存储器件。 存储器集线器包括耦合到每个存储器设备的存储器控​​制器，耦合到相应处理器或存储器模块的链路接口以及将任何存储器控制器耦合到任何链路接口的交叉开关。

公开(公告)号：US08266501B2

公开(公告)日：2012-09-11

申请号：US12569412

申请日：2009-09-29

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G11C29/00

CPC分类号： G06F11/08 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1028 ,  G06F11/108

摘要： The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

摘要翻译： 本公开包括用于基于条带的存储器操作的方法和设备。 一种方法实施例包括在多个存储器件的存储卷上写入第一条带中的数据。 通过在多个存储器件的存储卷上的第二条带的一部分中写入更新的数据来更新第一条带的一部分。 第一条纹的部分无效。 第一条纹的无效部分和第一条纹的剩余部分被保持直到第一条带被回收。 还公开了其它方法和装置。

公开(公告)号：US08200884B2

公开(公告)日：2012-06-12

申请号：US13163974

申请日：2011-06-20

申请人： Terry R. Lee ,  Joseph M. Jeddeloh

发明人： Terry R. Lee ,  Joseph M. Jeddeloh

IPC分类号： G06F12/06

CPC分类号： G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

摘要： A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

摘要翻译： 计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。 存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

公开(公告)号：US08117371B2

公开(公告)日：2012-02-14

申请号：US13230165

申请日：2011-09-12

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F13/36

CPC分类号： G06F13/4022 ,  G06F13/4234 ,  G06F13/4247 ,  Y10S370/912

摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

摘要翻译： 系统存储器包括存储器集线器控制器，存储器集线器控制器可访问的存储器模块以及具有耦合到存储器模块并且还具有对存储器模块的访问的处理器电路的扩展模块。 存储器集线器控制器通过存储器总线的第一部分耦合到存储器集线器，存储器总线的存储器请求来自存储器集线器控制器，并且来自存储器集线器的存储器响应被耦合。 存储器总线的第二部分将存储器集线器耦合到处理器电路，并且用于将来自处理器电路的存储器请求和由存储器集线器提供的存储器响应耦合到处理器电路。

公开(公告)号：US20110314199A1

公开(公告)日：2011-12-22

申请号：US13164156

申请日：2011-06-20

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F13/4009

摘要： A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

摘要翻译： 一种用于具有用于在系统存储器中执行DMA操作的DMA引擎的存储器模块的存储器集线器。 存储器集线器包括链接接口，用于接收对系统存储器的至少一个存储器件进行访问的存储器请求，并且还包括用于耦合到存储器件的存储器设备接口，存储器设备接口将存储器请求耦合到存储器件 用于访问至少一个存储设备。 用于选择性地耦合链路接口和存储器设备接口的开关还包括在存储器集线器中。 此外，直接存储器访问（DMA）引擎通过交换机耦合到存储器设备接口，以产生对至少一个存储器设备的访问以执行DMA操作的存储器请求。

公开(公告)号：US20110246743A1

公开(公告)日：2011-10-06

申请号：US13163974

申请日：2011-06-20

申请人： Terry R. Lee ,  Joseph M. Jeddeloh

发明人： Terry R. Lee ,  Joseph M. Jeddeloh

IPC分类号： G06F12/00

CPC分类号： G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

摘要： A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

公开(公告)号：US08019924B2

公开(公告)日：2011-09-13

申请号：US13032251

申请日：2011-02-22

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F13/36

CPC分类号： G06F13/4022 ,  G06F13/4234 ,  G06F13/4247 ,  Y10S370/912

摘要： A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.