Abstract:
A programmable frame router identifies different types of incoming frames and directs frames for processing to a processing engine or to a processor. The programmable frame router operates at the transport layer and receives frames from the link layer. The frame router stores programmable frame routing attributes that are used to identify where the frame is to be sent for processing based on information included in the frame[cl].
Abstract:
An expander device is configurable to identify itself as an end device and not an edge expander device. Other embodiments are also described and claimed.
Abstract:
In one embodiment, an apparatus may include a plurality of ports capable of being coupled to a plurality of devices via an associated plurality of communication links, the links being compliant with Serial Attached Small Computer Systems Interface (SAS) protocol. The apparatus may further include circuitry to provide selectable communication control between at least a first device and at least a second device of the plurality of devices. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
Abstract:
Provided are a method and device for address assignment for adaptor interfaces. An initial configuration is maintained assigning multiple local interfaces to one initial local address. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address.
Abstract:
An expander device is configurable to identify itself as an end device and not an edge expander device. Other embodiments are also described and claimed.
Abstract:
A method and apparatus for managing task context are provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.
Abstract:
Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
Abstract:
Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
Abstract:
In one embodiment, an apparatus may include a plurality of ports capable of being coupled to a plurality of devices via an associated plurality of communication links, the links being compliant with Serial Attached Small Computer Systems Interface (SAS) protocol. The apparatus may further include circuitry to provide selectable communication control between at least a first device and at least a second device of the plurality of devices. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
Abstract:
A state machine encoded in state machine instructions is stored in non-volatile memory, and loaded into volatile memory in a hardware engine for use by the hardware engine upon power up or reset. Storing the state machine for a phy reset sequence in non-volatile memory coupled to the hardware engine allows protocol modifications to the state machine to be performed in the non-volatile memory.