公开(公告)号：US20120250750A1

公开(公告)日：2012-10-04

申请号：US13435945

申请日：2012-03-30

Applicant: Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S. Harish Krishnan ,  Gururaj Padaki

Inventor： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S. Harish Krishnan ,  Gururaj Padaki

IPC: H04B17/00

CPC classification number: H04L27/0014 ,  H04L2027/003 ,  H04L2027/0065

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract translation: 用于降低用于频谱形状的多通信标准的输入信号的载波频偏（CFO）和符号定时偏移（STO）的实现复杂度的系统和方法。 该系统通过用移位器替换乘法器来实现。 该系统包括CFO估计块，STO估计块和提取输入信号的较低频带边沿和上边带边缘的频带提取块。 STO估计块包括（i）计算采样定时误差值的采样误差产生块，以及（ii）估计与采样定时误差值对应的频率误差和相位误差的锁相环块。 CFO估计块包括（i）产生载波偏移误差值的载波偏移误差产生块，和（ii）用于执行滤波操作的泄漏平均块。

公开(公告)号：US08103889B2

公开(公告)日：2012-01-24

申请号：US12335137

申请日：2008-12-15

Applicant: Parag Naik

Inventor： Parag Naik

IPC: G06F1/00

CPC classification number: G06F1/32 ,  G06F9/30

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract translation: 方法和设备，包括计算机程序产品，实现和使用技术来降低微处理器的功耗。 对微处理器的指令集中的一个或多个信号转换进行分析。 发生概率分配给指令集中的每个指令。 基于指令的出现概率，将二进制操作码分配给每个指令。 具有最高出现概率的指令被分配为需要较少信号转换的操作代码。 结果，微处理器的功耗降低了。

公开(公告)号：US07480809B2

公开(公告)日：2009-01-20

申请号：US11251586

申请日：2005-10-13

Applicant: Parag Naik

Inventor： Parag Naik

IPC: G06F1/00

CPC classification number: G06F1/32 ,  G06F9/30

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract translation: 方法和设备，包括计算机程序产品，实现和使用技术来降低微处理器的功耗。 对微处理器的指令集中的一个或多个信号转换进行分析。 发生概率分配给指令集中的每个指令。 基于指令的出现概率，将二进制操作码分配给每个指令。 具有最高出现概率的指令被分配为需要较少信号转换的操作代码。 结果，微处理器的功耗降低了。

公开(公告)号：US20080118006A1

公开(公告)日：2008-05-22

申请号：US11874337

申请日：2007-10-18

Applicant: S. Harish Krishnan ,  Parag Naik

Inventor： S. Harish Krishnan ,  Parag Naik

IPC: H04L27/22

CPC classification number: H04L27/2662 ,  H04L27/2607 ,  H04L27/2665

Abstract: At a receiver incoming coded OFDM Symbol Data are passed through a Coarse Symbol Timing Synchronization module to determine the approximate start of the symbol. In one embodiment this is accomplished through correlation. The symbol is then passed through an FFT (2K or 8K, depending on the mode desired by the receiver). Since the Coarse Symbol Timing Synchronization module only determines an approximate start point of the symbol, a process of fine synchronization is used to adjust this approximate start point and determine a more accurate start point of the symbol. In this manner, the receiver is enabled to process COFDM symbols in DVB-T transmissions (where the symbols include a cyclic prefix to overcome echoes). One output of an FFT operation is magnitude. Magnitude is used for Channel Estimation (or Channel Correction). Another output of an FFT operation is phase discontinuity or rotations. Phase discontinuities are used in a fine synchronization process to determine the number of phase discontinuities. Phase discontinuity data of the symbol is passed through an N-Point FFT.

Abstract translation: 在接收机输入的OFDM符号数据被传送通过粗符号定时同步模块来确定符号的大致开始。 在一个实施例中，这是通过相关来实现的。 然后，该符号通过FFT（2K或8K，取决于接收机所需的模式）。 由于粗符号定时同步模块仅确定符号的近似开始点，因此使用精细同步的过程来调整该近似起始点并确定符号的更准确的起始点。 以这种方式，接收机能够处理DVB-T传输中的COFDM符号（其中符号包括循环前缀以克服回声）。 FFT运算的一个输出是幅度。 幅度用于信道估计（或信道校正）。 FFT运算的另一个输出是相位不连续或旋转。 相位不连续性用于精细同步过程以确定相位不连续性的数量。 符号的相位不连续数据通过N点FFT。

公开(公告)号：US09372770B2

公开(公告)日：2016-06-21

申请号：US13909426

申请日：2013-06-04

Applicant: Karthick Gururaj ,  Sandeep Pendharkar ,  Parag Naik ,  Ragesh Thottathil Ramachandran ,  Deepanjan Kar

Inventor： Karthick Gururaj ,  Sandeep Pendharkar ,  Parag Naik ,  Ragesh Thottathil Ramachandran ,  Deepanjan Kar

IPC: G06F11/263

CPC classification number: G06F11/263 ,  G06F11/2635

Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyzes the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

Abstract translation: 提供了一个验证硬件平台的系统。 该系统包括存储一个或多个测试规范的数据库，一个基于（i）从设备驱动器生成器获得的设备驱动程序生成目标图像的编译器，（ii）与平台无关的目标应用程序代码，（iii）内核 来源和（iv）运行时环境以及软件驱动的验证生成器，其分析运行时规范和设备编程规范，并且基于（a）一个或多个测试规范生成（i）一个或多个测试用例， 和（b）设备编程规范，以及（ii）基于测试用例的控制软件。 测试用例包括特定于硬件平台的配置。 基于（i）在硬件平台上执行目标图像和控制软件，以及（ii）一个或多个测试用例来验证硬件平台。

公开(公告)号：US08676140B2

公开(公告)日：2014-03-18

申请号：US13434671

申请日：2012-03-29

Applicant: Subramanian Harish Krishnan ,  Parag Naik ,  Abdul Aziz ,  Subrahmanya Kondageri Shankaraiah

Inventor： Subramanian Harish Krishnan ,  Parag Naik ,  Abdul Aziz ,  Subrahmanya Kondageri Shankaraiah

IPC: H04B1/16

CPC classification number: H03G3/3078 ,  H03G3/3068

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract translation: 提供一种用于控制接收机的RF增益的系统，其减少了将输入信号电平维持在最佳动态范围所花费的时间。 该系统包括接收射频（RF）信号并将RF信号下变频为中频（IF）信号的调谐器和解调器。 调谐器包括射频可编程增益放大器（RF_VGA），滤波器和IF可编程增益放大器（IF_VGA）。 解调器包括模数转换器（ADC）和自动增益控制（AGC）单元，其（i）接收IF_VGA的数字信号和IF增益。 ADC在过采样条件下对滤波的IF信号进行采样，以获得包括带内信号和带外信号的过采样信号。 AGC单元（ii）控制RF_VGA，IF_VGA和（iii）测量RF信号的RF能量。

公开(公告)号：US08665976B2

公开(公告)日：2014-03-04

申请号：US13436022

申请日：2012-03-30

Applicant: Shrinivas Bhat ,  Vishwakumara Kayargadde ,  Parag Naik

Inventor： Shrinivas Bhat ,  Vishwakumara Kayargadde ,  Parag Naik

IPC: H04K1/10

CPC classification number: H04L27/2665 ,  H04L27/2032 ,  H04L27/2679

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver system for improved pilotless detection of symbol boundary of a received OFDM symbols using M-ary Phase Shift Keying (M-PSK) modulated carriers as a cost function. The OFDM receiver includes a symbol boundary detection block that detects a symbol boundary of the received OFDM symbols. The symbol boundary detection block detects the symbol boundary by computing a cost function of a second order moment of the M-PSK modulated carriers. The receiver system detects the symbol boundary for unknown information on the received OFDM symbols.

Abstract translation: 一种正交频分复用（OFDM）接收机系统，用于使用M相移相键控（M-PSK）调制载波作为成本函数来改进对接收的OFDM符号的符号边界的无监督检测。 OFDM接收机包括检测接收的OFDM符号的符号边界的符号边界检测块。 符号边界检测块通过计算M-PSK调制载波的二阶矩的成本函数来检测符号边界。 接收机系统检测接收的OFDM符号上的未知信息的符号边界。

公开(公告)号：US08611471B2

公开(公告)日：2013-12-17

申请号：US13435945

申请日：2012-03-30

Applicant: Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S Harish Krishnan ,  Gururaj Padaki

Inventor： Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  S Harish Krishnan ,  Gururaj Padaki

IPC: H04L27/00

CPC classification number: H04L27/0014 ,  H04L2027/003 ,  H04L2027/0065

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract translation: 用于降低用于频谱形状的多通信标准的输入信号的载波频偏（CFO）和符号定时偏移（STO）的实现复杂度的系统和方法。 该系统通过用移位器替换乘法器来实现。 该系统包括CFO估计块，STO估计块和提取输入信号的较低频带边沿和上边带边缘的频带提取块。 STO估计块包括（i）计算采样定时误差值的采样误差产生块，以及（ii）估计与采样定时误差值对应的频率误差和相位误差的锁相环块。 CFO估计块包括（i）产生载波偏移误差值的载波偏移误差产生块，和（ii）用于执行滤波操作的泄漏平均块。

公开(公告)号：US08605225B2

公开(公告)日：2013-12-10

申请号：US13433819

申请日：2012-03-29

Applicant: Sunil Hosur Ramesh ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

Inventor： Sunil Hosur Ramesh ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

IPC: H04N5/50

CPC classification number: H04N21/4384 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N21/42676 ,  H04N21/4345

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

Abstract translation: 提供了一种用于多个广播电视频道之间更快的频道切换时间的电视（TV）接收机，具有用于多个解调标准的整个解调周期中的延迟降低。 电视接收机包括从广播系统接收广播电视频道的调谐器，执行调谐操作，并且在频道扫描操作期间为每个广播电视频道设置期望的频率。 解调器解调每个广播电视频道，并且在频道扫描操作期间获取每个广播电视频道的一个或多个采集频道参数。 应用处理器经由低吞吐量接口耦合到解调器。 当信道状态从第一状态切换到第二状态时，应用处理器对解调器上的存储器映射寄存器执行读取操作和采集通道参数的写入操作。

公开(公告)号：US20120252389A1

公开(公告)日：2012-10-04

申请号：US13434671

申请日：2012-03-29

Applicant: Subramanian Harish Krishnan ,  Parag Naik ,  Abdul Aziz ,  Subrahmanya Kondageri Shankaraiah

Inventor： Subramanian Harish Krishnan ,  Parag Naik ,  Abdul Aziz ,  Subrahmanya Kondageri Shankaraiah

IPC: H04B1/16

CPC classification number: H03G3/3078 ,  H03G3/3068

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract translation: 提供一种用于控制接收机的RF增益的系统，其减少了将输入信号电平维持在最佳动态范围所花费的时间。 该系统包括接收射频（RF）信号并将RF信号下变频为中频（IF）信号的调谐器和解调器。 调谐器包括射频可编程增益放大器（RF_VGA），滤波器和IF可编程增益放大器（IF_VGA）。 解调器包括模数转换器（ADC）和自动增益控制（AGC）单元，其（i）接收IF_VGA的数字信号和IF增益。 ADC在过采样条件下对滤波的IF信号进行采样，以获得包括带内信号和带外信号的过采样信号。 AGC单元（ii）控制RF_VGA，IF_VGA和（iii）测量RF信号的RF能量。