公开(公告)号：US08644429B2

公开(公告)日：2014-02-04

申请号：US13447089

申请日：2012-04-13

Applicant: Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padki ,  Santosh Billava

Inventor： Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padki ,  Santosh Billava

IPC: H04L27/06

CPC classification number: H04B1/001

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract translation: 提供了一种宽带接收机，通过对数字域中的输入信号进行滤波来选择和解调具有单扫描频谱感测的输入信号，以实现提高的选择性和灵敏度。 输入信号包括一个或多个窄带射频（RF）信号。 宽带接收机包括将一个或多个窄带RF信号下变换成一个或多个IF信号的宽带调谐器。 模数转换器（ADC）将一个或多个IF信号转换成一个或多个数字信号。 滤波器拒绝来自一个或多个数字信号的带外信号以实现改进的选择性。 数控振荡器（NCO）基于从频谱选择控制单元获得的相位值，从数字信号中选择至少一个窄带数字信号。 解调器解调窄带数字信号以获得解调的数字信号。

公开(公告)号：US20130326275A1

公开(公告)日：2013-12-05

申请号：US13909426

申请日：2013-06-04

Applicant: Karthick Gururaj ,  Sandeep Pendharkar ,  Parag Naik ,  Ragesh Thottathil Ramachandran ,  Deepanjan Kar

Inventor： Karthick Gururaj ,  Sandeep Pendharkar ,  Parag Naik ,  Ragesh Thottathil Ramachandran ,  Deepanjan Kar

IPC: G06F11/263

CPC classification number: G06F11/263 ,  G06F11/2635

Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

Abstract translation: 提供了一个验证硬件平台的系统。 该系统包括存储一个或多个测试规范的数据库，一个基于（i）从设备驱动器生成器获得的设备驱动程序生成目标图像的编译器，（ii）与平台无关的目标应用程序代码，（iii）内核 来源和（iv）运行时环境以及软件驱动的验证生成器，其分析运行时规范和设备编程规范，并且基于（a）一个或多个测试规范生成（i）一个或多个测试用例， 和（b）设备编程规范，以及（ii）基于测试用例的控制软件。 测试用例包括特定于硬件平台的配置。 基于（i）在硬件平台上执行目标图像和控制软件，以及（ii）一个或多个测试用例来验证硬件平台。

公开(公告)号：US20120250799A1

公开(公告)日：2012-10-04

申请号：US13436022

申请日：2012-03-30

Applicant: Shrinivas Bhat ,  Vishwakumara Kayargadde ,  Parag Naik

Inventor： Shrinivas Bhat ,  Vishwakumara Kayargadde ,  Parag Naik

IPC: H04L27/22 ,  H04J11/00

CPC classification number: H04L27/2665 ,  H04L27/2032 ,  H04L27/2679

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver system for improved pilotless detection of symbol boundary of a received OFDM symbols using M-ary Phase Shift Keying (M-PSK) modulated carriers as a cost function is provided. The OFDM receiver includes a symbol boundary detection block that detects a symbol boundary of the received OFDM symbols. The symbol boundary detection block detects the symbol boundary by computing cost function of second order moment of the M-PSK modulated carriers. The receiver system is capable of detecting the symbol boundary for unknown information on said received OFDM symbols and thus increases throughput per given transmission bandwidth of a modulation scheme.

Abstract translation: 提供了一种正交频分复用（OFDM）接收机系统，用于使用M-phase相移键控（M-PSK）调制载波作为成本函数来改进对接收的OFDM符号的符号边界的无引导检测。 OFDM接收机包括检测接收的OFDM符号的符号边界的符号边界检测块。 符号边界检测块通过计算M-PSK调制载波的二阶矩的成本函数来检测符号边界。 接收机系统能够检测所接收的OFDM符号上的未知信息的符号边界，从而增加调制方案的给定传输带宽的吞吐量。

公开(公告)号：US20120249887A1

公开(公告)日：2012-10-04

申请号：US13433819

申请日：2012-03-29

Applicant: Sunil HR ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

Inventor： Sunil HR ,  Gururaj Padaki ,  Abdul Aziz ,  Parag Naik

IPC: H04N5/455

CPC classification number: H04N21/4384 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N21/42676 ,  H04N21/4345

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

Abstract translation: 提供了一种用于多个广播电视频道之间更快的频道切换时间的电视（TV）接收机，具有用于多个解调标准的整个解调周期中的延迟降低。 电视接收机包括从广播系统接收广播电视频道的调谐器，执行调谐操作，并且在频道扫描操作期间为每个广播电视频道设置期望的频率。 解调器解调每个广播电视频道，并且在频道扫描操作期间获取每个广播电视频道的一个或多个采集频道参数。 应用处理器经由低吞吐量接口耦合到解调器。 当信道状态从第一状态切换到第二状态时，应用处理器对解调器上的存储器映射寄存器执行读取操作和采集通道参数的写入操作。

公开(公告)号：US20060101297A1

公开(公告)日：2006-05-11

申请号：US11251586

申请日：2005-10-13

Applicant: Parag Naik

Inventor： Parag Naik

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F9/30

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

公开(公告)号：US08812569B2

公开(公告)日：2014-08-19

申请号：US13462116

申请日：2012-05-02

Applicant: Parag Naik ,  Anindya Saha ,  Gururaj Padaki ,  Subrahmanya Kondageri Shankaraiah ,  Saurabh Mishra

Inventor： Parag Naik ,  Anindya Saha ,  Gururaj Padaki ,  Subrahmanya Kondageri Shankaraiah ,  Saurabh Mishra

IPC: G06F17/10 ,  G06F7/38

CPC classification number: H03H21/0012 ,  H03H2021/007 ,  H03H2021/0072 ,  H03H2218/10

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract translation: 提供一种实现数字滤波器的方法。 该方法包括（a）通过测量输入数据样本的前导零或一个之间的距离以及输入数据样本的尾随零来确定输入信号的输入数据样本的位宽。 输入数据样本是通过以预定义的时间间隔对输入信号进行采样而获得的，（b）基于输入数据样本的位宽的第一概率分布函数（PDF））获得具有可变位宽的位宽乘数 ，（c）基于输入数据样本的位宽和滤波器系数的位宽分配输入数据样本和滤波器系数到位宽乘法器的一个位宽倍数，以及（d） 在一个位宽乘数上执行乘法和累加（MAC）运算的乘法运算，以产生数字滤波器的输出。

公开(公告)号：US08788549B2

公开(公告)日：2014-07-22

申请号：US13461902

申请日：2012-05-02

Applicant: Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

Inventor： Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

IPC: G06F7/00 ,  G06F7/38 ,  G06F7/483

CPC classification number: G06F7/483

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract translation: 提供了一种用于通过检测中央处理单元中的输入信号的动态范围来计算块浮点缩放因子的系统，而没有额外的开销周期。 该系统包括动态范围监测单元，其通过窥探输出写入数据和输入信号的输入存储器读取数据来检测输入信号的动态范围。 动态范围监视单元包括运行的最大计数单元，其存储前导零和前导零的计数的最小值，以及存储尾随零计数的最小值的运行最小计数。 基于前导零和前导零的计数的最小值和尾随零的计数来检测动态范围。 该系统还包括一个缩放因子计算模块，它根据动态范围计算块浮点（BFP）缩放因子。

公开(公告)号：US08571119B2

公开(公告)日：2013-10-29

申请号：US13435326

申请日：2012-03-30

Applicant: Parag Naik ,  Anindya Saha ,  Hemant Mallapur ,  Sunil Hr ,  Gururaj Padaki

Inventor： Parag Naik ,  Anindya Saha ,  Hemant Mallapur ,  Sunil Hr ,  Gururaj Padaki

IPC: H04L27/00

CPC classification number: H04B1/0007 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/27 ,  H03M13/2906 ,  H03M13/2936 ,  H03M13/6522 ,  H04H40/18 ,  H04N5/455 ,  H04N5/46 ,  H04N21/2383 ,  H04N21/4382

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract translation: 能够支持用于输入信号的调制，解调和转换的多种通信标准和平台的软件定义无线电（SDR）子系统。 SDR子系统包括信号调节簇（SCC）单元，其包括适于基于采样的信号处理的信号调节CPU，包括适用于基于块的信号处理的信号处理CPU的信号处理簇（SPC）单元，以及信道编解码器 集群（CCC）单元执行信道编码或信道解码操作。

公开(公告)号：US20090177902A1

公开(公告)日：2009-07-09

申请号：US12335137

申请日：2008-12-15

Applicant: Parag Naik

Inventor： Parag Naik

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/32 ,  G06F9/30

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract translation: 方法和设备，包括计算机程序产品，实现和使用技术来降低微处理器的功耗。 对微处理器的指令集中的一个或多个信号转换进行分析。 发生概率分配给指令集中的每个指令。 基于指令的出现概率，将二进制操作码分配给每个指令。 具有最高出现概率的指令被分配为需要较少信号转换的操作代码。 结果，微处理器的功耗降低了。

公开(公告)号：US20120269300A1

公开(公告)日：2012-10-25

申请号：US13447089

申请日：2012-04-13

Applicant: Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padaki ,  Santosh Billava

Inventor： Subramanian Harish Krishnan ,  Saurabh Mishra ,  Parag Naik ,  Subrahmanya Kondageri Shankaraiah ,  Gururaj Padaki ,  Santosh Billava

IPC: H04B1/10

CPC classification number: H04B1/001

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract translation: 提供了一种宽带接收机，通过对数字域中的输入信号进行滤波来选择和解调具有单扫描频谱感测的输入信号，以实现提高的选择性和灵敏度。 输入信号包括一个或多个窄带射频（RF）信号。 宽带接收机包括将一个或多个窄带RF信号下变换成一个或多个IF信号的宽带调谐器。 模数转换器（ADC）将一个或多个IF信号转换成一个或多个数字信号。 滤波器拒绝来自一个或多个数字信号的带外信号以实现改进的选择性。 数控振荡器（NCO）基于从频谱选择控制单元获得的相位值，从数字信号中选择至少一个窄带数字信号。 解调器解调窄带数字信号以获得解调的数字信号。