公开(公告)号：US5619686A

公开(公告)日：1997-04-08

申请号：US154744

申请日：1993-11-18

申请人： Allan Lin ,  Jay Deng

发明人： Allan Lin ,  Jay Deng

IPC分类号： H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H04L25/493 ,  H04L25/52 ,  G06F1/06

CPC分类号： H04L7/0091 ,  H04L25/493 ,  H03L7/0995 ,  H04L7/0008

摘要： A data source circuit and a complementary data acquisition circuit which can transmit and receive data at a higher rate than a conventional data source circuit which uses similar fabrication technology. A data source circuit of the present invention has an input for receiving a periodic source clock signal having a period T; a synchronization signal generator for generating, based on said downstream-clock signal, a series of one or more periodic synchronization signals having periods substantially equal to T, each synchronization signal being delayed from a previous synchronization signal; and a transmitter for transmitting one or more sub-words of a multi-bit data word, each sub-word having one or more bits, separate ones of said one or more sub-words being transmitted responsive to separate progressively delayed combined pairs of said synchronization signals. In a preferred embodiment of the present invention particularly suited for use in a point to point (e.g. a ring-type) data network, an acquisition circuit and a source circuit are integrated as a receiver/retransmission node.

摘要翻译： 数据源电路和互补数据采集电路，其能够以比使用类似的制造技术的常规数据源电路更高的速率发送和接收数据。 本发明的数据源电路具有用于接收具有周期T的周期性源时钟信号的输入端; 同步信号发生器，用于基于所述下行时钟信号产生一系列具有基本上等于T的周期的周期性同步信号，每个同步信号从先前的同步信号延迟; 以及发送器，用于发送多比特数据字的一个或多个子字，每个子字具有一个或多个比特，所述一个或多个子字中的不同的子字响应于分离的逐渐延迟的所述组合对而被发送 同步信号 在特别适用于点对点（例如环型）数据网络的本发明的优选实施例中，采集电路和源电路被集成为接收机/重传节点。