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    RENDERING USING RAY TRACING TO GENERATE A VISIBILITY STREAM
    11.
    发明申请
    RENDERING USING RAY TRACING TO GENERATE A VISIBILITY STREAM 有权
    渲染利用雷达追踪生成可见性流

    公开(公告)号：US20160364901A1

    公开(公告)日：2016-12-15

    申请号：US14738535

    申请日：2015-06-12

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Juraj Obert ,  Hitendra Mohan Gangani ,  Avinash Seetharamaiah

    IPC: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40

    CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/40

    Abstract: A method and apparatus for ray tracing may include a method, manufacture and apparatus for ray tracing that may include dividing a render target into a plurality of bins. Next, a visibility pass is performed using ray tracing to generate a visibility stream such that the visibility stream indicates, for each bin of the plurality of bins, which primitives are visible in the bin. Then, for at least one bin of the plurality of bins, each primitive in the bin that is indicated in the visibility stream as being visible in the bin is rendered.

    Abstract translation: 用于光线跟踪的方法和装置可以包括用于光线跟踪的方法，制造和装置，其可以包括将呈现目标划分成多个仓。 接下来，使用光线跟踪来执行可见度通过以产生可见性流，使得可见度流针对多个区段中的每个仓表示哪些图元在仓中可见。 然后，对于多个箱中的至少一个箱，呈​​现在可见度流中在箱中可见的在仓中的每个基元在仓中可见。

    Intra-frame timestamps for tile-based rendering
    12.
    发明授权
    Intra-frame timestamps for tile-based rendering 有权
    基于瓦片的渲染的帧内时间戳

    公开(公告)号：US09449410B2

    公开(公告)日：2016-09-20

    申请号：US14044396

    申请日：2013-10-02

    Applicant: QUALCOMM Incorporated

    Inventor： Christopher Paul Frascati ,  Hitendra Mohan Gangani ,  Avinash Seetharamaiah

    IPC: G09G5/00 ,  G06F15/00 ,  G06T1/00 ,  G06T11/40 ,  G06T1/20 ,  G06T15/04 ,  G06T11/00 ,  G06T15/00

    CPC classification number: G06T11/40 ,  G06T1/20 ,  G06T11/001 ,  G06T15/005 ,  G06T15/04

    Abstract: This disclosure describes techniques for supporting intra-frame timestamps in a graphics system that performs tile-based rendering. The techniques for supporting intra-frame timestamps may involve generating a timestamp value that is indicative of a point in time based on a plurality of per-bin timestamp values that are generated by a graphics processing unit (GPU) while performing tile-based rendering for a graphics frame. The timestamp value may be a function of at least two of the plurality of per-bin timestamp values. The timestamp value may be generated by a central processing unit (CPU), the GPU, another processor, or any combination thereof. By using per-bin timestamp values to generate timestamp values for intra-frame timestamp requests, intra-frame timestamps may be supported by a graphics system that performs tile-based rendering.

    Abstract translation: 本公开描述了在执行基于瓦片的呈现的图形系统中支持帧内时间戳的技术。 用于支持帧内时间戳的技术可以包括基于由图形处理单元（GPU）生成的多个每个时间戳时间戳来生成指示时间点的时间戳值，同时执行基于瓦片的渲染 一个图形框架。 时间戳值可以是多个每个时间戳值中的至少两个的函数。 时间戳值可以由中央处理单元（CPU），GPU，另一个处理器或其任何组合生成。 通过使用每个时间戳的值来生成帧内时间戳请求的时间戳值，帧内时间戳可以由执行基于瓦片的呈现的图形系统来支持。

    Reordering of command streams for graphical processing units (GPUs)
    13.
    发明授权
    Reordering of command streams for graphical processing units (GPUs) 有权
    图形处理单元（GPU）的命令流重排序

    公开(公告)号：US09384522B2

    公开(公告)日：2016-07-05

    申请号：US13776067

    申请日：2013-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T1/20 ,  G06T15/00 ,  G09G5/36

    CPC classification number: G06T1/20 ,  G06T15/005 ,  G09G5/363

    Abstract: In general, techniques are described for analyzing a command stream that configures a graphics processing unit (GPU) to render one or more render targets. A device comprising a processor may perform the techniques. The processor may be configured to analyze the command stream to determine a representation of the one or more render targets defined by the command stream. The processor may also be configured to, based on the representation of the render targets, and identify one or more rendering inefficiencies that will occur upon execution of the command stream by the GPU. The processor may also be configured to re-order one or more commands in the command stream so as to reduce the identified rendering inefficiencies that will occur upon execution of the command stream by the GPU.

    Abstract translation: 通常，描述用于分析配置图形处理单元（GPU）以渲染一个或多个渲染目标的命令流的技术。 包括处理器的设备可以执行这些技术。 处理器可以被配置为分析命令流以确定由命令流定义的一个或多个渲染目标的表示。 处理器还可以被配置为基于渲染目标的表示，并且识别由GPU执行命令流时将发生的一个或多个渲染无效率。 处理器还可以被配置为重新命令命令流中的一个或多个命令，以便减少由GPU执行命令流时将发生的所识别的渲染效率低下。

    Optimized multi-pass rendering on tiled base architectures
    14.
    发明授权
    Optimized multi-pass rendering on tiled base architectures 有权
    在平铺基础架构上优化多遍渲染

    公开(公告)号：US09280845B2

    公开(公告)日：2016-03-08

    申请号：US14154996

    申请日：2014-01-14

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T15/00

    CPC classification number: G06T1/20 ,  G06T15/005

    Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.

    Abstract translation: 本公开提供了用于基于瓦片的架构上的多路径渲染的系统和方法，包括使用图形处理单元（GPU）执行查询遍，所述查询遍与GPU一起执行基于查询遍的条件真传递而不执行 刷新操作，与GPU一起执行基于查询传递的条件错误通过而不执行刷新操作，并且响应于执行条件真传递和条件伪传递，执行与GPU的冲洗操作。

    COMMAND INSTRUCTION MANAGEMENT
    15.
    发明申请
    COMMAND INSTRUCTION MANAGEMENT 有权
    指挥指导管理

    公开(公告)号：US20140354660A1

    公开(公告)日：2014-12-04

    申请号：US14027816

    申请日：2013-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Murat Balci ,  Christopher Paul Frascati ,  Avinash Seetharamaiah

    IPC: G06T1/20

    CPC classification number: G06T1/20 ,  G06F9/3881 ,  G06F9/50 ,  G06F9/5022 ,  G06T1/60

    Abstract: Techniques are described for writing commands to memory units of a chain of memory units of a command buffer. The techniques may write the commands, and if during the writing, it is determined that there is not sufficient space in the chain of memory unit, the techniques may flush previously confirmed commands. If after the writing, the techniques determine that there is not sufficient space in an allocation list for the handles associated with the commands, the techniques may flush previously confirmed commands.

    Abstract translation: 描述了将命令写入命令​​缓冲器的存储器单元链的存储器单元的技术。 这些技术可以写入命令，并且如果在写入期间确定存储器单元链中没有足够的空间，则这些技术可以刷新先前确认的命令。 如果在写入之后，这些技术确定在与命令相关联的句柄的分配列表中没有足够的空间，该技术可以冲洗以前确认的命令。

    RENDERING GRAPHICS DATA USING VISIBILITY INFORMATION
    16.
    发明申请
    RENDERING GRAPHICS DATA USING VISIBILITY INFORMATION 有权
    使用可见性信息渲染图形数据

    公开(公告)号：US20140198119A1

    公开(公告)日：2014-07-17

    申请号：US13744111

    申请日：2013-01-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： Avinash Seetharamaiah ,  Murat Balci ,  Christopher Paul Frascati ,  Andrew E. Gruber

    IPC: G06T11/40

    CPC classification number: G06T11/40 ,  G06T15/005

    Abstract: In some examples, aspects of this disclosure relate to a method for rendering an image. For example, the method includes generating visibility information indicating visible primitives of the image. The method also includes rendering the image using a binning configuration, wherein the binning configuration is based on the visibility information.

    Abstract translation: 在一些示例中，本公开的方面涉及用于呈现图像的方法。 例如，该方法包括产生指示图像的可见原始图像的可见性信息。 该方法还包括使用合并配置呈现图像，其中分档配置基于可见性信息。

    PACKING MULTIPLE SHADER PROGRAMS ONTO A GRAPHICS PROCESSOR
    17.
    发明申请
    PACKING MULTIPLE SHADER PROGRAMS ONTO A GRAPHICS PROCESSOR 有权
    将多个阴影程序包装到图形处理器上

    公开(公告)号：US20130169642A1

    公开(公告)日：2013-07-04

    申请号：US13708118

    申请日：2012-12-07

    Applicant: QUALCOMM Incorporated

    Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Joseph Blankenship

    IPC: G06T15/80

    CPC classification number: G06T15/80 ,  G06F9/445 ,  G06F9/44594 ,  G06T1/20 ,  G06T1/60 ,  G06T7/40 ,  G06T11/00 ,  G06T15/04 ,  G06T15/83 ,  G06T17/10 ,  G06T17/20

    Abstract: This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (GPU). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time. In addition, various techniques for evicting shader programs from an on-chip shader program instruction memory are described.

    Abstract translation: 本公开描述了将共同着色器程序类型的多个着色器程序打包到图形处理单元（GPU）上的技术。 这些技术可以包括例如使得共同着色器程序类型的多个着色器程序被加载到图形处理器的片上着色器程序指令存储器中，使得多个着色器程序中的每个着色器程序驻留在 片上着色器程序指令存储器在公共时间点。 此外，描述了用于从片上着色器程序指令存储器驱逐着色器程序的各种技术。

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