公开(公告)号：US20220068360A1

公开(公告)日：2022-03-03

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON ,  Jason CHENG ,  Yandong GAO ,  Chulmin JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/02

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US20210255243A1

公开(公告)日：2021-08-19

申请号：US16794105

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Changho JUNG ,  Chulmin JUNG

IPC: G01R31/3181 ,  G01J1/18 ,  G01R31/317

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

公开(公告)号：US20210098057A1

公开(公告)日：2021-04-01

申请号：US16911313

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Chulmin JUNG ,  Percy DADABHOY

IPC: G11C11/419 ,  H03K3/3562 ,  H04M1/02

Abstract: A memory is provided with a pre-charge circuit/write driver that pre-charges a bit line in a bit line pair responsive to a master latch output signal from a master latch in a data buffer. A slave latch associated with the master latch is prevented from becoming open by a clock controller during write operations for the memory.

公开(公告)号：US20170278563A1

公开(公告)日：2017-09-28

申请号：US15077636

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu KWOK ,  Changho JUNG

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.

公开(公告)号：US20150221346A1

公开(公告)日：2015-08-06

申请号：US14173788

申请日：2014-02-05

Applicant: QUALCOMM Incorporated

Inventor： Rakesh VATTIKONDA ,  Frederick NGURE ,  Changho JUNG

IPC: G11C5/02 ,  G11C7/00

CPC classification number: G11C5/02 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1116

Abstract: A multiport bitcell apparatus includes a plurality of word lines for enabling writing and reading operations. The word lines include a first set of word lines extending across the bitcell on a first metal layer. The word lines further include a second set of word lines extending across the bitcell on a second metal layer. The word lines further include a third set of word lines extending across the bitcell on both the first metal layer and the second metal layer. The third set of word lines may include a first word line that extends on a first metal track and a second metal track, and a second word line that extends on the second metal track and a third metal track. The first metal layer may be an M2 layer and the second metal layer may be an M3 layer.

Abstract translation: 多端口位单元装置包括用于使能写入和读取操作的多个字线。 字线包括在第一金属层上跨越位单元延伸的第一组字线。 字线还包括在第二金属层上跨越位单元延伸的第二组字线。 字线还包括在第一金属层和第二金属层两者上跨越位单元延伸的第三组字线。 第三组字线可以包括在第一金属轨道和第二金属轨道上延伸的第一字线，以及在第二金属轨道和第三金属轨道上延伸的第二字线。 第一金属层可以是M2层，第二金属层可以是M3层。

公开(公告)号：US20230223075A1

公开(公告)日：2023-07-13

申请号：US18175023

申请日：2023-02-27

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Arun Babu PALLERLA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/413 ,  H03K19/20

CPC classification number: G11C11/419 ,  G11C11/413 ,  H03K19/20

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US20230093852A1

公开(公告)日：2023-03-30

申请号：US17448846

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Chulmin JUNG

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C5/14 ,  H03K19/21

Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

公开(公告)号：US20220068373A1

公开(公告)日：2022-03-03

申请号：US17008476

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Percy DADABHOY ,  Arun Babu PALLERLA

IPC: G11C11/419

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. To assist the charge-transfer by the charge-transfer transistor, a first and second cross-coupled transistor are coupled between the bit line and a complement bit line.

公开(公告)号：US20220068371A1

公开(公告)日：2022-03-03

申请号：US17001993

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON

IPC: G11C11/419

Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.

公开(公告)号：US20220068369A1

公开(公告)日：2022-03-03

申请号：US17002010

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.