公开(公告)号：US20200020624A1

公开(公告)日：2020-01-16

申请号：US16030936

申请日：2018-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Joan Rey Villarba BUOT ,  Soumyadipta BASU ,  Charles David PAYNTER

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A chip package substrate and methods for fabricating the chip package substrate. An exemplary chip package substrate generally includes a first substrate and a second substrate embedded in the first substrate and having a plurality of layered traces embedded therein.

公开(公告)号：US20150294945A1

公开(公告)日：2015-10-15

申请号：US14251236

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Siamak FAZELPOUR ,  Charles David PAYNTER ,  Ryan David LANE

IPC: H01L23/58 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4885 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01R13/6471

Abstract: The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Abstract translation: 本公开涉及半导体封装中的引脚布局。 本公开的一个实施例提供了一种隔离一组差分引脚对的菱形共享参考引脚布局。 差分信号引脚对被配置为使得由垂直信号引脚对形成的轴线与横向信号引脚对形成的轴线正交并相互平分。