公开(公告)号：US11715679B2

公开(公告)日：2023-08-01

申请号：US16597808

申请日：2019-10-09

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Woochan Kim ,  Vivek Kishorechand Arora

IPC分类号： H01L23/538 ,  H01L23/495 ,  H01L25/065 ,  H02M3/156 ,  H01L25/07 ,  H01L25/16 ,  H01L21/48 ,  H01L23/48 ,  H02M1/00

CPC分类号： H01L23/49575 ,  H01L21/4885 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5387 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/165 ,  H02M3/156 ,  H02M1/0012

摘要： A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

公开(公告)号：US10020237B2

公开(公告)日：2018-07-10

申请号：US14925274

申请日：2015-10-28

申请人： Infineon Technologies AG

发明人： Alexander Hoehn ,  Georg Borghoff

IPC分类号： H01L23/02 ,  H01L23/15 ,  H01L23/053 ,  H01L21/48 ,  H01L23/498 ,  H05K5/00

CPC分类号： H01L23/053 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/4885 ,  H01L21/52 ,  H01L23/08 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H05K5/0008 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided.

公开(公告)号：US20180076111A1

公开(公告)日：2018-03-15

申请号：US15264292

申请日：2016-09-13

申请人： International Business Machines Corporation

发明人： Mark Delorman Schultz

IPC分类号： H01L23/367 ,  H01L21/48

CPC分类号： H01L23/3677 ,  F28D9/0031 ,  H01L21/4882 ,  H01L21/4885 ,  H01L23/467 ,  H01L23/473 ,  Y10T428/12507

摘要： A device can comprise a plurality of layers stacked and bonded on one another, wherein at least one layer of the plurality of layers comprises: a first active region comprising first pin portions positioned in a first planar arrangement; and a second active region comprising second pin portions positioned in a second planar arrangement, wherein the second planar arrangement is different from the first planar arrangement. The device can also comprise a conformable layer adjacent to at least one of the plurality of layers.

公开(公告)号：US20170117260A1

公开(公告)日：2017-04-27

申请号：US15332991

申请日：2016-10-24

申请人： Invensas Corporation

发明人： Ashok S. Prabhu ,  Rajesh Katkar

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L25/105 ,  H01L21/4846 ,  H01L21/4885 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2021/60 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

摘要： Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

公开(公告)号：US20160372338A1

公开(公告)日：2016-12-22

申请号：US14901878

申请日：2013-12-02

申请人： Jiangsu Changjiang Electronics Technology Co., Ltd

发明人： Steve Xin Liang ,  Chih-Chung Liang ,  Yu-Bin Lin ,  Yaqin Wang ,  Youhai Zhang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L21/4832 ,  H01L21/48 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/4885 ,  H01L21/4889 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

摘要翻译： 提供了一种包括水晶芯片的水平切片三维系统级金属电路板结构，包括金属基板框架; 金属基板框架在其中设置有基岛和销; 基岛的前面设有芯片; 芯片的前表面通过金属线连接到销的前表面; 导电柱设置在销的前表面或后表面上; 基岛的周边区域，基岛和引脚之间的区域，引脚之间的区域，基岛上的区域和引脚，基岛和引脚之下的区域以及芯片的外部 ，金属线和导电柱都用模塑料包封。

公开(公告)号：US20160148863A1

公开(公告)日：2016-05-26

申请号：US14549846

申请日：2014-11-21

申请人： International Business Machines Corporation

发明人： Fen Chen ,  Mukta G. Farooq ,  John M. Safran

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L21/4885 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3-D) integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of non-contiguous dummy walls patterned in a corresponding dielectric level around a circuit wire keep out zone (KOZ). The non-contiguous dummy walls are formed in the circuit wire KOZ and have an outer side and an opposing inner side that extend along a first direction to define a length. A circuit wire segment is located at a first metal level and a second circuit wire segment is located at a second metal level different from the first metal level. The first and second metal levels are located adjacent the inner side of at least one non-contiguous dummy wall.

摘要翻译： 包括形成在基板上的多个堆叠电介质层的三维（3-D）集成电路布线包括在电路线保持区（KOZ）周围的相应电介质层中图案化的多个不连续的虚设壁。 不连续的虚设壁形成在电路线KOZ中，具有沿着第一方向延伸以限定长度的外侧和相对的内侧。 电路线段位于第一金属水平处，并且第二电路线段位于不同于第一金属水平的第二金属水平处。 第一和第二金属水平位于邻近至少一个不连续的虚拟壁的内侧。

公开(公告)号：US20150294945A1

公开(公告)日：2015-10-15

申请号：US14251236

申请日：2014-04-11

申请人： QUALCOMM Incorporated

发明人： Siamak FAZELPOUR ,  Charles David PAYNTER ,  Ryan David LANE

IPC分类号： H01L23/58 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/4885 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01R13/6471

摘要： The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

摘要翻译： 本公开涉及半导体封装中的引脚布局。 本公开的一个实施例提供了一种隔离一组差分引脚对的菱形共享参考引脚布局。 差分信号引脚对被配置为使得由垂直信号引脚对形成的轴线与横向信号引脚对形成的轴线正交并相互平分。

公开(公告)号：US20140051245A1

公开(公告)日：2014-02-20

申请号：US14113664

申请日：2012-05-03

申请人： Nicolas Karst ,  Simon Perraud

发明人： Nicolas Karst ,  Simon Perraud

IPC分类号： H01L21/288 ,  H01L21/48

CPC分类号： H01L21/288 ,  B05C3/18 ,  B05C5/001 ,  B05C5/0254 ,  B05C11/04 ,  H01L21/4885 ,  H01L31/0322 ,  H01L31/18 ,  Y02E10/541 ,  Y02P70/521

摘要： The device for knife coating a layer of ink based on copper and indium on a substrate includes a supply tank of an ink, said tank collaborating with a coating knife. In addition, the device includes means that allow the ink, the substrate and the coating knife to be kept at different and increasing respective temperatures.

摘要翻译： 用于在基板上涂覆基于铜和铟的一层油墨的装置包括油墨供应罐，所述罐与涂布刀协作。 此外，该装置包括允许墨，基底和涂布刀保持不同并增加相应温度的装置。

公开(公告)号：US08618659B2

公开(公告)日：2013-12-31

申请号：US13462158

申请日：2012-05-02

申请人： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

发明人： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC分类号： H01L23/48

CPC分类号： H01L21/4885 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

摘要翻译： 微电子组件包括具有第一表面和远离第一表面的第二表面的衬底。 微电子元件覆盖在第一表面上，并且第一导电元件暴露在第一表面和第二表面中的一个处。 一些第一导电元件电连接到微电子元件。 线接合具有连接到远离基板和基座的导电元件和端表面的基部，每个引线接合限定在基部和端表面之间延伸的边缘表面。 封装层从第一表面延伸并填充引线键合之间的空间，使得引线键合被封装层分离。 引线键合的未封装的部分由未被封装层覆盖的引线接合端表面的至少部分限定。

公开(公告)号：US20130334054A1

公开(公告)日：2013-12-19

申请号：US13916817

申请日：2013-06-13

申请人： Commissariat A L'Energie Atomique Et Aux Energie Alternatives

发明人： Cyril CHAPPAZ GILLOT ,  Solenn BERSON ,  Valentina IVANOVA ,  Raul SALAZAR ROMERO

IPC分类号： H01L21/48

CPC分类号： H01L21/4885 ,  C25D3/38 ,  C25D9/08

摘要： A method for forming, on a conductive or semiconductor substrate, nanowires based on CuSCN, including the steps of: preparing an aqueous electrolytic solution from a Cu(II) salt having a concentration lower than 120 mM, a Cu(II) complexing agent from the aminocarboxylic acid family, and a thiocyanate salt, the solution having a pH ranging between 0.1 and 3; electrochemically depositing the aqueous electrolytic solution on the substrate.

摘要翻译： 一种在导电或半导体衬底上形成基于CuSCN的纳米线的方法，包括以下步骤：从浓度低于120mM的Cu（II）盐制备电解质水溶液，制备Cu（II）络合剂， 氨基羧酸系和硫氰酸盐，该溶液的pH范围在0.1和3之间; 在基材上电化学沉积含水电解液。