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公开(公告)号:US20200169266A1
公开(公告)日:2020-05-28
申请号:US16202723
申请日:2018-11-28
Applicant: QUALCOMM Incorporated
Inventor: Shahin MEHDIZAD TALEIE , Behnam SEDIGHI , Dongwon SEO , Parisa MAHMOUDIDARYAN , Bhushan Shanti ASURI , Sang-June PARK , Shrenik PATEL
IPC: H03M1/66
Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.
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公开(公告)号:US20180358883A1
公开(公告)日:2018-12-13
申请号:US15710704
申请日:2017-09-20
Applicant: QUALCOMM Incorporated
Inventor: Nitz SAPUTRA , Sang Min LEE , Dongwon SEO , Vinay KUNDUR , Behnam SEDIGHI , Honghao JI
CPC classification number: H02M1/00 , H02J5/00 , H02M1/143 , H02M2001/0006 , H02M2001/0012
Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.
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