公开(公告)号：US20230336187A1

公开(公告)日：2023-10-19

申请号：US17659531

申请日：2022-04-18

Applicant: QUALCOMM Incorporated

Inventor： Nitz SAPUTRA ,  Ashok SWAMINATHAN

IPC: H03M1/76 ,  H03K17/687 ,  H03M1/78

CPC classification number: H03M1/785 ,  H03K17/687 ,  H03M1/76

Abstract: Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

公开(公告)号：US20250125792A1

公开(公告)日：2025-04-17

申请号：US18485882

申请日：2023-10-12

Applicant: QUALCOMM Incorporated

Inventor： Nitz SAPUTRA ,  Sameer WADHWA

IPC: H03K3/012 ,  G06F13/42 ,  H03K17/687

Abstract: A transmitter includes driver slices coupled to its output. Each driver slice includes a first differential predriver that is selectively enabled and disabled by a first switch based on a control code configuration. A second differential predriver provides a first differential buffered data signal to a first group of driver slices when the second differential predriver is enabled. A second switch enables the second differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the first group of driver slices. A third differential predriver provides a second differential buffered data signal to a second group of driver slices when the third differential predriver is enabled. A third switch enables the third differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice in the second group of driver slices.

公开(公告)号：US20190288722A1

公开(公告)日：2019-09-19

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti ASURI ,  Krishnaswamy THIAGARAJAN ,  Ashok SWAMINATHAN ,  Shahin MEHDIZAD TALEIE ,  Yen-Wei CHANG ,  Vinod PANIKKATH ,  Sameer Vasantlal VORA ,  Ayush MITTAL ,  Tonmoy BISWAS ,  Sy-Chyuan HWU ,  Zhilong TANG ,  Ibrahim CHAMAS ,  Ping Wing LAI ,  Behnam SEDIGHI ,  Dongwon SEO ,  Nitz SAPUTRA

IPC: H04B1/04 ,  H04B1/00 ,  H04L27/20

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20240429937A1

公开(公告)日：2024-12-26

申请号：US18338708

申请日：2023-06-21

Applicant: QUALCOMM Incorporated

Inventor： Xiahan ZHOU ,  Haibo FEI ,  Nitz SAPUTRA ,  Andrew WEIL

IPC: H03M1/74

Abstract: Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

公开(公告)号：US20230299757A1

公开(公告)日：2023-09-21

申请号：US17654916

申请日：2022-03-15

Applicant: QUALCOMM Incorporated

Inventor： Negar RASHIDI ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN

IPC: H03K5/05 ,  H03M1/82

CPC classification number: H03K5/05 ,  H03M1/82

Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

公开(公告)号：US20240204795A1

公开(公告)日：2024-06-20

申请号：US18068941

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ashok SWAMINATHAN ,  Nitz SAPUTRA ,  Negar RASHIDI ,  Shahin MEHDIZAD TALEIE ,  Chinmaya MISHRA ,  Dongwon SEO ,  Jong Hyeon PARK ,  Sang-June PARK

IPC: H03M1/66 ,  H03M1/82

CPC classification number: H03M1/665 ,  H03M1/82

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

公开(公告)号：US20230097708A1

公开(公告)日：2023-03-30

申请号：US17448461

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Parisa MAHMOUDIDARYAN ,  Nitz SAPUTRA ,  Dongwon SEO ,  Shahin MEHDIZAD TALEIE

IPC: H03M1/06

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

公开(公告)号：US20220352899A1

公开(公告)日：2022-11-03

申请号：US17244384

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Nitz SAPUTRA ,  Ashok SWAMINATHAN ,  Andrew WEIL

IPC: H03M1/66 ,  H03K19/21 ,  H04B1/00

Abstract: Certain aspects of the present disclosure provide a digital-to-analog conversion circuit. The digital-to-analog conversion circuit generally includes a detection circuit configured to detect digital transitions in a digital input signal. The digital-to-analog conversion circuit also includes a clock-gating circuit having an input coupled to an output of the detection circuit. The clock-gating circuit is configured to gate a clock signal for the digital-to-analog conversion circuit based on an output signal from the detection circuit.

公开(公告)号：US20240204753A1

公开(公告)日：2024-06-20

申请号：US18068837

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Peter GAZZERRO ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN ,  Osama ELHADIDY ,  Bo YANG

IPC: H03H11/04 ,  H03M1/06 ,  H03M1/66 ,  H04B1/04

CPC classification number: H03H11/0461 ,  H03M1/0626 ,  H03M1/66 ,  H04B1/04

Abstract: Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

公开(公告)号：US20240014824A1

公开(公告)日：2024-01-11

申请号：US17811706

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Sumant RAMPRASAD ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN

IPC: H03M1/08

CPC classification number: H03M1/08

Abstract: Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.