公开(公告)号：US20230306233A1

公开(公告)日：2023-09-28

申请号：US18103428

申请日：2023-01-30

Applicant: QUALCOMM Incorporated

Inventor： Marinus Willem VAN BAALEN ,  Brian KAHNE ,  Eric Wayne MAHURIN ,  Tijmen Pieter Frederik BLANKEVOORT ,  Andrey KUZMIN ,  Andrii SKLIAR ,  Markus NAGEL

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: A processor-implemented method includes bit shifting a binary representation of a neural network parameter. The neural network parameter has fewer bits, b, than a number of hardware bits, B, supported by hardware that processes the neural network parameter. The bit shifting effectively multiplies the neural network parameter by 2B-b. The method also includes dividing a quantization scale by 2B-b to obtain an updated quantization scale. The method further includes quantizing the bit shifted binary representation with the updated quantization scale to obtain a value for the neural network parameter.

公开(公告)号：US20210241070A1

公开(公告)日：2021-08-05

申请号：US17165648

申请日：2021-02-02

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN

IPC: G06N3/04

Abstract: A device includes one or more processors configured to retrieve a first block of data, the data corresponding to array of values arranged along at least a first dimension and a second dimension, to retrieve at least a portion of a second block of the data, and to perform a first hybrid convolution operation that applies a filter across the first block and at least the portion of the second block to generate output data. The output data includes a first accumulated block and at least a portion of a second accumulated block. The one or more processors are also configured to store the first accumulated block as first output data. The portion of the second block is adjacent to the first block along the first dimension and the portion of the second accumulated block is adjacent to the first accumulated block along the second dimension.

公开(公告)号：US20210240394A1

公开(公告)日：2021-08-05

申请号：US17166263

申请日：2021-02-03

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Hitesh Kumar GUPTA ,  Ahmad RADAIDEH

IPC: G06F3/06

Abstract: A device includes a scoreboard and a processor. The scoreboard includes scoreboard entries configured to store information regarding one or more uncompleted memory access operations. The scoreboard also includes a dependency matrix configured to store dependency information corresponding to the scoreboard entries. The processor is configured to retrieve a first memory access instruction that indicates a first address range of a first memory access operation, and to add an indication of the first memory access instruction to a first scoreboard entry. The processor is further configured to, based on determining that the first address range at least partially overlaps a second address range associated with a second scoreboard entry that corresponds to a second memory access instruction, set an element of the dependency matrix to have a has-dependency value indicating a dependency of the first scoreboard entry on the second scoreboard entry.

公开(公告)号：US20170083066A1

公开(公告)日：2017-03-23

申请号：US14860715

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Sanjay Bhagawan PATIL ,  Martin Pierre SAINT-LAURENT

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/329 ,  Y02D10/24

Abstract: Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.

公开(公告)号：US20170046156A1

公开(公告)日：2017-02-16

申请号：US14826199

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Lucian CODRESCU ,  Erich James PLONDKE ,  David HOYLE ,  Mao ZENG ,  Kim-Chyan GAN

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30003 ,  G06F9/3004

Abstract: Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.

Abstract translation: 系统和方法属于查找表的条目。 处理器接收一个或多个单指令多数据（SIMD）指令，包括指定索引的第一子集的第一SIMD指令。 使用交叉开关查找表条目的第一个子集，并使用索引的第一个子集。 第一SIMD指令的第一矢量输出基于交叉开关的输出是否属于表条目的期望子集。 类似地，第二，第三和第四SIMD指令指定相应的第二，第三和第四索引子集，以使用横杠来查找剩余的表条目。 交叉开关的大小基于用于查找表条目的索引子集中的索引数。

公开(公告)号：US20170046153A1

公开(公告)日：2017-02-16

申请号：US14826196

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/00 ,  G06F7/5443 ,  G06F9/30036 ,  G06F17/16

Abstract: Systems and methods relate to multiply-and-horizontal-reduce operations, implemented in a digital filter, for example. A single instruction multiple data (SIMD) instruction comprising a first vector comprising M+C multiplicand elements, wherein M and C are positive integers and a second vector comprising M+C corresponding multiplier elements, wherein the C multiplier elements have a value of 1, is received. Using M multipliers in a processor, M multiplications of M multiplicand elements with corresponding M multiplier elements which do not include the C multiplier elements whose values are 1, are performed to generate M products. The C multiplicand elements whose corresponding C multiplier elements have values of 1 are added to or vertically accumulated with the M products.

Abstract translation: 例如，系统和方法涉及在数字滤波器中实现的乘法和水平减少运算。 一种单指令多数据（SIMD）指令，包括包含M + C个被乘数的第一向量，其中M和C是正整数，以及包括M + C对应的乘法器元件的第二向量，其中C乘法器元件具有值1， 被收到。 在处理器中使用M个乘法器，执行M个被乘数元素与不包括其值为1的C个乘法器元素的相应M个乘法器元素的M次乘法以产生M个乘积。 其对应的C乘数元素具有值1的C个被乘数元素被添加到M个乘积或垂直累积。