公开(公告)号：US20170046156A1

公开(公告)日：2017-02-16

申请号：US14826199

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Eric Wayne MAHURIN ,  Lucian CODRESCU ,  Erich James PLONDKE ,  David HOYLE ,  Mao ZENG ,  Kim-Chyan GAN

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30003 ,  G06F9/3004

Abstract: Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.

Abstract translation: 系统和方法属于查找表的条目。 处理器接收一个或多个单指令多数据（SIMD）指令，包括指定索引的第一子集的第一SIMD指令。 使用交叉开关查找表条目的第一个子集，并使用索引的第一个子集。 第一SIMD指令的第一矢量输出基于交叉开关的输出是否属于表条目的期望子集。 类似地，第二，第三和第四SIMD指令指定相应的第二，第三和第四索引子集，以使用横杠来查找剩余的表条目。 交叉开关的大小基于用于查找表条目的索引子集中的索引数。

公开(公告)号：US20170371739A1

公开(公告)日：2017-12-28

申请号：US15192981

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Erich James PLONDKE

IPC: G06F11/10 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F11/1048 ,  G06F9/30145 ,  G06F11/10 ,  G06F11/1032 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and method of error checking for instructions method of error checking for instructions include an assembler for creating an instruction packet with one or more instructions, determining if a parity of the instruction packet matches a predesignated parity, and if the parity of the instruction packet does not match the predesignated parity, using a bit of the instruction packet to change parity of the instruction packet to match the predesignated parity. The instruction packet with the predesignated parity is stored in a memory, and may eventually be retrieved by a processor for execution. If there is an error in the instruction packet retrieved from the memory, the error is detected based on comparing the parity of the instruction packet to the predesignated parity.

公开(公告)号：US20160246534A1

公开(公告)日：2016-08-25

申请号：US14627433

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward KOOB ,  Erich James PLONDKE ,  Jiajin TU

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F1/32 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/30076 ,  G06F12/08 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/13

Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.

Abstract translation: 监视内存的处理器访问。 监视包括识别对本地存储器或非本地存储器的访问。 基于监视，处理器从非本地存储器访问模式切换到本地存储器访问模式。

公开(公告)号：US20160246731A1

公开(公告)日：2016-08-25

申请号：US14626925

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward KOOB ,  Erich James PLONDKE ,  Jiajin TU

IPC: G06F12/10 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F1/32 ,  G06F11/073 ,  G06F11/079 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/502 ,  G06F2212/684 ,  Y02D10/13

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Abstract translation: 翻译后备缓冲器（TLB）存储翻译条目。 翻译条目包括虚拟地址，物理地址和存储器本地/非本地标志。 当处理器处于低功耗/本地存储器模式时，接收到虚拟地址。 匹配的翻译条目具有本地/非本地标志。 在指示本地存储器外的匹配转换条目的物理地址的本地/非本地标志时，生成访问范围外存储器访问异常。