公开(公告)号：US09020458B2

公开(公告)日：2015-04-28

申请号：US13901320

申请日：2013-05-23

Applicant: QUALCOMM Incorporated

Inventor： Jeremy Mark Goldblatt

IPC: H04B1/28 ,  H04L25/03 ,  H03D7/14 ,  H03D7/16 ,  H03D7/18

CPC classification number: H04L25/03878 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165 ,  H03D7/18 ,  H03D2200/0088

Abstract: A passive mixer with channel impedance equalization is disclosed. In an exemplary embodiment, an apparatus includes replica devices configured to generate replica output signals and an error amplifier configured to generate bias signals based on the replica output signals. The bias signals are configured to equalize on-state channel impedances associated with a mixer.

Abstract translation: 公开了一种具有通道阻抗均衡的无源混频器。 在示例性实施例中，一种装置包括被配置为产生副本输出信号的复制设备和被配置为基于复制输出信号产生偏置信号的误差放大器。 偏置信号被配置为均衡与混频器相关联的通态阻抗。

公开(公告)号：US20140376683A1

公开(公告)日：2014-12-25

申请号：US13926923

申请日：2013-06-25

Applicant: QUALCOMM Incorporated

Inventor： Jeremy Mark Goldblatt ,  Devavrata Vasant Godbole ,  Hsuanyu Pan

IPC: H03K21/17

CPC classification number: H03K21/17 ,  H03K5/15033 ,  H03K23/425

Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.

Abstract translation: 高速和低功率分配器包括四个动态锁存器环，互锁电路和四个输出反相器。 每个锁存器具有第一动态节点M和第二动态节点N.互锁电路耦合到M个节点。 基于接收到的一个或多个M个节点信号，互锁电路选择性地控制M个模式中的一个或多个的逻辑值，使得随着时间的推移，当分频器被计时时，N个节点上的信号中只有一个为低 在给定的时间。 输出反相器产生从分频器输出的N个节点信号的反相版本，作为低相位噪声25％占空比输出信号I，IB，Q和QB。 在一个具体示例中，每个锁存器具有八个晶体管，不超过八个晶体管。 分离器快速自动地从错误的状态干扰中恢复。

公开(公告)号：US20140103984A1

公开(公告)日：2014-04-17

申请号：US13654328

申请日：2012-10-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jeremy Mark Goldblatt ,  Sameer V. Vora

IPC: H03K5/15

Abstract: Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverters may be coupled to at least two dynamic logic cells of the plurality of dynamic logic cells. Each inverter may be configured to output a twenty-five percent duty cycle clock signal.

Abstract translation: 示例性实施例涉及用于产生正交时钟信号的系统，方法和装置。 设备可以包括多个动态逻辑单元和多个逆变器。 多个反相器的每个反相器可以耦合到多个动态逻辑单元中的至少两个动态逻辑单元。 每个逆变器可以被配置为输出二十五％的占空比时钟信号。