公开(公告)号：US20210281234A1

公开(公告)日：2021-09-09

申请号：US16812294

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/01 ,  H01L49/02 ,  H01F17/00 ,  H01L27/06

Abstract: An improved filter for high frequency, such as 5G wireless communication, may include inductor-Q improvement and reduced die-size with a hybrid 3D-inductor integration. In some examples, the inductors may be formed using an IPD and a fan-out package. For instance, a first multilayer substrate comprises a plurality of metal insulator metal (MIM) capacitors formed using various layers (e.g., M1 and M2) and a first portion of the 3D inductors, and a second multilayer substrate comprises at least a second portion of the 3D inductors. The 3D inductors may be electrically coupled to the MIM capacitors to form at least one filter network.

公开(公告)号：US20210234526A1

公开(公告)日：2021-07-29

申请号：US16750625

申请日：2020-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/38 ,  H01Q1/22 ,  H01Q1/52 ,  H04B1/40

Abstract: Impedance matching transceivers may include a tuning circuit to match the transceiver module impedance to the housing conditions. In some examples, the impedance matching is controlled by tuning-circuits that may be integrated into a transceiver module by using a fan-out package (FO PKG). One example of a tuning circuit may include a switch to isolate the parallel capacitors, such that when the switch is on or closed the parallel capacitors are active.

公开(公告)号：US20190081027A1

公开(公告)日：2019-03-14

申请号：US16185635

申请日：2018-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh KUMAR ,  Chin-Kwan KIM ,  Milind SHAH

IPC: H01L25/10 ,  H01L23/66 ,  H01L23/552 ,  H01L25/065 ,  H04W4/80 ,  H04W4/00 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/16

Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.

公开(公告)号：US20230260947A1

公开(公告)日：2023-08-17

申请号：US18303345

申请日：2023-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM ,  Abdolreza LANGARI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L23/3157 ,  H01L21/565 ,  H01L23/481 ,  H01L2924/01014 ,  H01L2924/1205 ,  H01L2924/14

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

公开(公告)号：US20220223585A1

公开(公告)日：2022-07-14

申请号：US17144411

申请日：2021-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L27/08 ,  H01L25/10 ,  H01L49/02

Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

公开(公告)号：US20210376810A1

公开(公告)日：2021-12-02

申请号：US16884891

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H9/05 ,  H01L41/053 ,  H01L41/047 ,  H03H9/145 ,  H01L25/04 ,  H03H9/64 ,  H01L41/23 ,  H03H3/02 ,  H03H9/02

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

公开(公告)号：US20210280540A1

公开(公告)日：2021-09-09

申请号：US16812882

申请日：2020-03-09

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64 ,  H01L21/56

Abstract: A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device. The second package includes a passive device, a second encapsulation layer encapsulating the passive device, a second redistribution portion comprising a second plurality of redistribution interconnects, wherein the second redistribution portion is coupled to the passive device and the second encapsulation layer, and a second plurality of contacts coupled to the passive device, wherein the second plurality of contacts is coupled to the first plurality of contacts from the first package.

公开(公告)号：US20210280507A1

公开(公告)日：2021-09-09

申请号：US16810589

申请日：2020-03-05

Applicant: QUALCOMM Incorporated

Inventor： Manuel ALDRETE ,  Milind SHAH ,  Srikanth KULKARNI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/64 ,  H01L21/56 ,  H01L21/48

Abstract: A package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.

公开(公告)号：US20210098567A1

公开(公告)日：2021-04-01

申请号：US16798161

申请日：2020-02-21

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.